Considering INPUT as CLOCK in Xilinx Synthesis

[manchal]

THIS IS FINAL SYNTHESIS REPORT OF MY DESIGN. iT HAS"a[7:0]" AS ITS INPUT,but it's taking a[1] as clock,Dont knw WHY.PLS HELP.
SECONDLY,if the same design(which took input as clock,on its own) without clock gives, timing report as Minimum period as well as Maximum combinational path delay,IS THE REPORT CORRECT??
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
a<1> | IBUF+BUFG | 1 |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found
Minimum input arrival time before clock: 2.805ns
Maximum output required time after clock: 7.550ns
Maximum combinational path delay: 10.859ns

 

[barry]

Without knowing anything else about your design it is impossible to determine why this signal is a clock.

 

[manchal]

//THIS is a design for BYPASSING MULTIPLIER.A condition is APPLIED ON INPUT I.E. "a".which is taken as CLOCK.
module en_column(a,b,sum);
parameter n=3;
input [n:0] a,b;
output [n+n+1:0] sum;
reg [n:0] p [n:0];
integer i,j;
reg [n:0] sm [n-1:0];
reg [n-1:0] s [n-1:0];
reg [n-1:0] c [n-1:0];
reg x [n-1:0];
reg q [n:0];
reg [n+n+1:0] sum;
integer k,jj=0,ii=0;
//partial product generation
always@(a or b)
begin
for(i=0;i<n+1;i = i+1)
for(j=0;j<n+1;j = j+1)
p[j] = a[j] & b;
end
//1st row of multiplier
always @*
begin
sum[0]=p[0][0];
for(k=0;k<n;k=k+1) begin
if(a[k]==1) begin //condition on input.
fa(p[ii][jj+1],p[ii+1][jj],0,s[ii][jj],c[ii][jj]); //task called full adder
muxsum (s[ii][jj],p[ii][jj+1],a[k],sm[ii][jj]); //task multipliexer
end
else begin
s[ii][jj]=0;
c[ii][jj]=0;
muxsum (s[ii][jj],p[ii][jj+1],a[k],sm[ii][jj]);
end
jj=jj+1;
end

 

[barry]

Sorry, I don't speak verilog.

 

[tariq786]

It seems you have not set up the constraints (pin assignments) of your design. That is why the tool is choosing whatever it feels like.

Learn how to do pin assignments in xilinx ise.

 

[manchal]

Tariq786 ,For all the designs which i implemented pin assignment was not required.Should pin assignment be done for all designs,through I/O PlanAhead N what difference does it makes to the synthesis report? What is its importance.?