code for reversing bits verilog

[krishna_1980]

verilog reverse bit order

HI

Can anyone know how to reverse bits in verilog. The code should be simpler (no functions pls and it should be min lines)

bye

Added after 1 hours 8 minutes:

and this is what i wrote

         case (m)

         0: 
         begin 
         tmp0[0] = mtxd_pad_o[3];
         tmp0[1] = mtxd_pad_o[2];
         tmp0[2] = mtxd_pad_o[1];
         tmp0[3] = mtxd_pad_o[0];
         $display("mtxd_pad_o IS %d and tmp0 is %d", mtxd_pad_o,tmp0);
         end
         
         1:  
         begin
         tmp1[0] = mtxd_pad_o[3];
         tmp1[1] = mtxd_pad_o[2];
         tmp1[2] = mtxd_pad_o[1];
         tmp1[3] = mtxd_pad_o[0];
         $display("mtxd_pad_o IS %d and tmp1 is %d", mtxd_pad_o,tmp1);
         end   

         2:
         begin
         tmp2[0] = mtxd_pad_o[3];
         tmp2[1] = mtxd_pad_o[2];
         tmp2[2] = mtxd_pad_o[1];
         tmp2[3] = mtxd_pad_o[0];
         $display("mtxd_pad_o IS %d and tmp2 is %d", mtxd_pad_o,tmp2);
         end
         
         3:
         begin
         tmp3[0] = mtxd_pad_o[3];
         tmp3[1] = mtxd_pad_o[2];
         tmp3[2] = mtxd_pad_o[1];
         tmp3[3] = mtxd_pad_o[0];
         $display("mtxd_pad_o IS %d and tmp3 is %d", mtxd_pad_o,tmp3);
         end
         endcase
	
	if (m==3)
	l=1;

	m=m+1;

end//forever

         length={tmp3,tmp2,tmp1,tmp0};

 

[aajizattari]

bit reverse verilog

WEll !!

A long time since tried such things

I hope

temp[3:0] = mtxd_pad_0[0:3]

will work

Check this and let me know!!! if My memory still works



and to make code look a little fine

temp = {mtxd_pad_0[0],mtxd_pad_0[1],mtxd_pad_0[2],mtxd_pad_0[3]};

This will work for sure

 

[krishna_1980]

verilog bit reverse

Hi

i have tried with all those things. It gives illegal part select error. have u tried with that code?
or just putting here

module reverse_bits();

reg [3:0] tmp;

reg [0:3] data;

initial
begin
data=4'b1010;
tmp[3:0]=data[0:3]; //if it is tmp [0:3] it says illegal range
$display("data %0b\t tmp %0b",data,tmp);
end

endmodule

 

[avimit]

verilog register bit order

Hi,
This works,
n'joy.

module reverse_bits(); 
parameter wi = 3;

reg [wi:0] tmp; 

reg [wi:0] data; 

integer ii;

initial 
begin 
data=4'b1110; 

for (ii=wi; ii >= 0; ii=ii-1)
  tmp[wi-ii]=data[ii];

$display("data %b\t tmp %b",data,tmp); 

#2 $finish;

end 

endmodule

Kr,
Avi
http://www.vlsiip.com

 

[krishna_1980]

reverse bit order verilog

thanks Mittal