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Co simulation of verilog of system C

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nix_24

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cadence ncsc

Hi

please share any info regarding the topic,how to start with cosimulkaton?what are the basic requirements to cosimulkate HDL with system C . what interface one should look for this purpose
 

skpatel73

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Just get a simulator that will do both SystemC and Verilog. I've used both Modelsim and Aldec for this.

The interface is simple...you just instantiate the SystemC piece as a verilog module in your testbench. Your simulator should come with a bunch of examples of how to do this.

Samir
 

maxsnail

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use cadence ncsc simulator
 

nix_24

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is there any doc/example to state how to do it step by step ,

i tried it this way say we have system files sys.cpp a cpp file where i am having an PLI interface with HDL and an i/o function which controls the output in sys.cpp . i co mplie/link this cpp files into an .so and then provide this to the simulator in run time {using modelsim }.??? it failed do to some undefined symbols during complie time and hence resulting in error while loading the design


any suggestions ???

Regards
NIX
 

s8319

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All of the help documents of the simulators that support co-simulation have the information that you need, for example , about the interface.......
 

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