CMOS voltage buffer for driving 500pF cap

[electronics_rama]

Hi,

I am designing a voltage reference buffer driving a huge capacitance of 500pF. My settling time specification, from the undershoot voltage to final voltage is less than 100ns. That means I need a high bandwidth buffer, but this cannot be achieved with class-A amplifier topology for the buffer.

So should I go ahead with class-AB structure for the buffer design or is there any other topology which meets my design specifications?

Thanks,
Rama

 

[D.A.(Tony)Stewart]

What is the voltage step input and current limit? Is it constant C=I*dt/dV or dynamic?

 

[Dominik Przyborowski]

For such high capacitive loads you need or multistage (3 or 4 stages) or a multipath architecture.
The two design examples:
https://ieeexplore.ieee.org/abstract/document/7164357/
https://ieeexplore.ieee.org/document/7289395/

 

[dick_freebird]

Options depend on other things such as DC impedance.
If C-only, perhaps an op amp buffer with an output series
resistance (in the usual C-driving way) could do the job.
Depends on the step -> slew rate -> current, and "how
close is close enough" (settling to 1/2 LSB maybe, but
how many bits and what signal range?). Maybe a current
feedback style for speed (if you are not being told what
technology you can and can't use).

Now voltage references don't usually do much slewing,
maybe once per power cycle, so what's with the "fast
settling" anyhow?

 

[electronics_rama]

What is the voltage step input and current limit? Is it constant C=I*dt/dV or dynamic?

Voltage step input is 900mV. Current limit is 150uA with 3V supply.

- - - Updated - - -

For such high capacitive loads you need or multistage (3 or 4 stages) or a multipath architecture.
The two design examples:
https://ieeexplore.ieee.org/abstract/document/7164357/
https://ieeexplore.ieee.org/document/7289395/

From these papers I can see that the bandwidth is very less as compared to the bandwidth requirement to achieve the given settling time of less than 100ns.

So, how about Class-AB architecture? What are your thoughts on using it as buffer which can drive huge cap loads.