Cmos inverter/nor/nand gates dimensions

[AMSA84]

Hi guys,

I'd like to know if someone can tell me which are the criteria do design a NOR gate in terms of MOSFETs dimensions. The tech is 130nm.

Should I use the minimum transistor sizes in all mosfets?

Thanks in advance.

 

[Dominik Przyborowski]

For equal rise/fall times You have to provide the same resistances for group of pfets and nfets of each gate. In first approximation the Wp/Wn =Kn/Kp for inverters. For nand gates the parallel connection of pfets should give you the same resistance as serial connection of nfets, while opposite for nor. The length should be set a minimum one (it's not true for radiation hardness designs) and width depends to load capacitance and maximum freuqency of your design.

 

[AMSA84]

Thanks.

There are any expressions where we can estimate in a first order analysis before simulate?

 

[Dominik Przyborowski]

The rise/fall time could be calculate from constant current charging/discharging load capacitance. The current value is VDD·Ron, where Ron is resistance of each transistor and is equal to:
\[R_{on}=\frac{1}{K W/L (V_{dd}-V_{th})}\]
The output voltage could be simply calculated as exponential function with time constant equal to Ron·Cload (small signall analysis) or by using slew rate equation SR=Vdd/(Ron·Cload) [V/s] which also gives You a time of linear charging load capacitance from ground to Vdd.

In fact I'm not sure which one gives better results

 

[erikl]

The current value is VDD·Ron

I'm sure you thought of VDD/Ron .

 

[Dominik Przyborowski]

Yes, yes. Of course Vdd/Ron. I solved Too much nodal equations with conductances instead of resistances ;-)

 

[AMSA84]

Thanks for the reply. I understand.

Allow me to ask another thing.

When we're designing a non overlap circuit, can we use different number of delay elements in the feedback path?

For example, on the 1st clock 2 inverters and in the 2nd clock 4 inverters?

Regarding the non overlap circuit, why we can only use a even number of delay lines? (2, 4, 6, etc).

 

[erikl]

Non-overlapping clock pulse generator

When we're designing a non overlap circuit, can we use different number of delay elements in the feedback path?
For example, on the 1st clock 2 inverters and in the 2nd clock 4 inverters?

Sure, you can do this. Creates some asymmetry re. clock pulse & non-overlapping time.

Regarding the non overlap circuit, why we can only use a even number of delay lines? (2, 4, 6, etc).

You always need an uneven (odd) number of inverting stages (180° phase shift) in total between clock input and feedback input, s. this figure: **broken link removed**