It's depend how we define short circuit here. With high enough supply peak current can be high as well.During the transition from high to low or low to high, when both P and N are briefly on, I thought there was a brief short-circuit path to ground.
Notice, that for example TTL circuits can be broken by low enough supply (due to forcing some devices in the active normal region and exponential nature of BJTs). Moreover, BJTs logic has nonzero steady current, while CMOS has leakage only if not switching. So, average current can be much lower. Also, MOS current is exponential only for low Vgs (in subthreshold).Do CMOS inverters never ever need source and drain resistors to limit this current, it's only BJT push-pull stages that require emitter current-limiting resistors?
Yes, might be but might be not.What if the gate signal were left on at mid-supply for several minutes and both P and N were on - might they be damaged?
Basically, transconductance of MOS transistors is much lower than BJTs - transfer characteristic slope is close to linear or weaker, while BJTs are exponential.Thickie question: Why is CMOS current limited, by RDS(on)?
The specification are in a sub µs range range, I doubt that they are related to power dissipation. IMHO primary purpose of maximum rise/fall time specifications is to guarantee proper signal edges. According to the quiescent current graphs given in the above linked 74HC user manuals, biasing inverter inputs near the logic threshold (mid supply in case of 74HC) causes considerable power dissipation but doesn't exceed the ratings.There is usually a maximum input rise/fall time specified for CMOS inputs to limit the duration of the overcurrent situation, I.e., average current.
From th Texas Instruments “ Implications of Slow or Floating CMOS inputs” app note:The specification are in a sub µs range range, I doubt that they are related to power dissipation. IMHO primary purpose of maximum rise/fall time specifications is to guarantee proper signal edges. According to the quiescent current graphs given in the above linked 74HC user manuals, biasing inverter inputs near the logic threshold (mid supply in case of 74HC) causes considerable power dissipation but doesn't exceed the ratings.
Ordinary CD4xxx logic ICs use tiny low current Mosfets. 74HCxxxx ICs produce much higher current.
The datasheet of a CD4069 inverter shows a typical "shoot-through" current of 1mA when the supply is 5V, is 4.5mA when the supply is 10V and is 11mA when the supply is 15V. Ordinary CD4069 inverters are used as linear amplifiers when they have negative feedback and have the input biased at half the supply voltage.
Hi,
from the document given in post#6:
* the current depends on supply voltage. (quite expectable)
* it is about 200uA at 3V Vcc.
Thus at 3V the series resistance is about 15 kOhms.
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An OPAMP ouput stage may be short circuit prove .. or not. It may be time limited or infinite. It may depend on ambient temperautre or not. The information is given in it´s datasheet.
It usually can drive some 10s of mA. Maybe cause some 100mW of dissipated power. You can feel the temperature rise.
200uA at 3V just gives 600uW of heat. Not noticable. Much less than an Opamp output stage.
Another difference between OPAMP and logic inverter is, that the OPAMP output is feedbacked. So an OPAMP output is not "weak". In opposite it is very low ohmic - driving immediately as much current as possible - trying to get the desired output voltage, until current becomes limited.
Klaus
"Linear amp graph"Hi,
Thanks. Where is that specific linear amplifier graph from, please?
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Hi Klaus,
I read the whole of the Nexperia app note you posted the link to yesterday (and the Slow or Floating Inputs danadakk posted), a lot of information to absorb...
So, in short, no. Op amp to logic was comparing apples and pears, whoops. Thank you.
I think from RCA or Harris a long time ago.Where is that specific linear amplifier graph from, please?
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