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[SOLVED] CMOS inverter basic questions

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d123

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Hi,

With reference to a CMOS inverter, e.g.

The CMOS Inverter Explained

During the transition from high to low or low to high, when both P and N are briefly on, I thought there was a brief short-circuit path to ground.

Do CMOS inverters never ever need source and drain resistors to limit this current, it's only BJT push-pull stages that require emitter current-limiting resistors?

What if the gate signal were left on at mid-supply for several minutes and both P and N were on - might they be damaged?
 

KlausST

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Hi,

In the link "figure2" the axis are wrong. Vi <--> Vo.
See the figure below, which is correct.

When the input voltage is somewhere in the midfle of VCC and GND then both Fets may be ON.
The current is limited.

This is well known.
The current sometimes is called "crowbar current".
Note: while it depends on input voltage ... the current is from VCC to GND. A increased supply current.

This usually is written in the datasheets. Example: Philips/NXP 74HC04 datasheet: it is called "deltaICC" or "additional supply current".
As this is common to most CMOS circuits, there is the recommendation for HIGH to be very close to VCC and LOW very close to GND.
Also the time from HIGH to LOW should be short.
Never leave such in input floating.
This is very urgent when you want to design very low power applications (battery powered).

Often bidirectiinal databusses are left floating when "idle". --> Not optimal for low power current consumption.
Better use weak drive, pull up, pull down or buskeeper.

Klaus
 
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Dominik Przyborowski

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During the transition from high to low or low to high, when both P and N are briefly on, I thought there was a brief short-circuit path to ground.
It's depend how we define short circuit here. With high enough supply peak current can be high as well.

Do CMOS inverters never ever need source and drain resistors to limit this current, it's only BJT push-pull stages that require emitter current-limiting resistors?
Notice, that for example TTL circuits can be broken by low enough supply (due to forcing some devices in the active normal region and exponential nature of BJTs). Moreover, BJTs logic has nonzero steady current, while CMOS has leakage only if not switching. So, average current can be much lower. Also, MOS current is exponential only for low Vgs (in subthreshold).
What if the gate signal were left on at mid-supply for several minutes and both P and N were on - might they be damaged?
Yes, might be but might be not.
Depends to supply. 4000 series operating with wide range of supply and you notice different current for 3V and for 12V for sure.
I don't know how reliability challenges are treated for CMOS logic COTS. In the IC important stuff are interconnections and electromigrations of metal paths, as within recommended supply operation range breakdown voltages are high enough.
 
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Hi,

Interesting, thank you. Crowbar = shoot-through = short-circuit. Never noticed 'additional supply current' field before in datasheets.

I have 'previous form' breaking TTL and discrete push-pull stages, unfortunately.

I need to do some revision and further reading, seeing both replies.

Thickie question: Why is CMOS current limited, by RDS(on)?

If someone were to make a discrete 'high power' (e.g. > 200mA or 1A, etc.) CMOS inverter, to avoid breadboard prototyping accidents would it be sensible/advisable to add current-limiting resistors to respective P drain and N source junction based on datasheet SOA curves, (or at the P source) or are those resistors theoretically never needed as the inverter would survive stupid (for example) 10-second to 10-minute input voltage mistakes?
 

Dominik Przyborowski

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Thickie question: Why is CMOS current limited, by RDS(on)?
Basically, transconductance of MOS transistors is much lower than BJTs - transfer characteristic slope is close to linear or weaker, while BJTs are exponential.

Look for the numbers. Assuming MOSFET parameters from spice models from 1st post link,
NMOS will conduct ≈0.5µA at 1V on gate (its Vth), ≈75µA at 2V, 320µA at 3V and 1.25mA at 5V.

While, hypothetic BJT conducting 1µA at 0.7V Vbe, would try to force 117mA at 1V and 4.66E+66 A at 5V on base - what of course mean that it is short circuit and we see only contact resistance which are limiting the current to order of 1A.
 
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Ordinary CD4xxx logic ICs use tiny low current Mosfets. 74HCxxxx ICs produce much higher current.
The datasheet of a CD4069 inverter shows a typical "shoot-through" current of 1mA when the supply is 5V, is 4.5mA when the supply is 10V and is 11mA when the supply is 15V. Ordinary CD4069 inverters are used as linear amplifiers when they have negative feedback and have the input biased at half the supply voltage.
 

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It's never a short circuit, rather two series channel
resistances each somewhat higher than "Rds(on)"
(full Vdd on gate, for that test condition, while the
Vdd/(series-sum) peak current is seen about Vdd/2
if the FETs are sized for equal drain current at full
gate drive).

Only in cases where you are concerned about the
channels "lighting up" beyond gate controlled Id,
would you consider adding extrinsic series resistance.
This is done for example in output drivers, putting
silicide-block and adding some G-D distance to
impose a "ballast" resistor ensuring drain current
is shared evenly among fingers in the event of some
overstress applied to the output, ESD being one.

In a well protected core you wouldn't need this
outside of some environments which don't bear
discussing here, and generally this would be
addressed more by bussing design for aggregate
max current @ speed.
 
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barry

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There is usually a maximum input rise/fall time specified for CMOS inputs to limit the duration of the overcurrent situation, I.e., average current.
 
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I agree that a 74HCxxx Cmos output has such a high output current that its linear time duration has a maximum allowed duration.
 
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There is usually a maximum input rise/fall time specified for CMOS inputs to limit the duration of the overcurrent situation, I.e., average current.
The specification are in a sub µs range range, I doubt that they are related to power dissipation. IMHO primary purpose of maximum rise/fall time specifications is to guarantee proper signal edges. According to the quiescent current graphs given in the above linked 74HC user manuals, biasing inverter inputs near the logic threshold (mid supply in case of 74HC) causes considerable power dissipation but doesn't exceed the ratings.
 
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Hi,

(I've run out of 'helped me's until this evening)

So, it's sort of similar to an op amp short-circuit parameter: 'harmless' within PD specifications and sensible ambient temperature for the device? ...But, best avoided as it will degrade the IC or transistor if done for longer than e.g. microseconds?

How would I calculate series-sum resistance for this complementary P and N in a soic (datasheet attached)? It's selected just for the example, it could be asked regarding any well-matched P and N devices.

I'm concluding, so far, from all these insightful comments, that for 'my friend' who makes breadboard mistakes sometimes, an external resistor is a must until they are sure of what they are doing when making/experimenting with discrete 'high-power' CMOS inverters, especially if they are unsure of how to calculate actual in-circuit series resistances of both transistors. Like stabilizers on a child's first bicycle until they can ride it without falling off.
 

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KlausST

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Hi,

from the document given in post#6:
* the current depends on supply voltage. (quite expectable)
* it is about 200uA at 3V Vcc.

Thus at 3V the series resistance is about 15 kOhms.

****
An OPAMP ouput stage may be short circuit prove .. or not. It may be time limited or infinite. It may depend on ambient temperautre or not. The information is given in it´s datasheet.
It usually can drive some 10s of mA. Maybe cause some 100mW of dissipated power. You can feel the temperature rise.

200uA at 3V just gives 600uW of heat. Not noticable. Much less than an Opamp output stage.
Another difference between OPAMP and logic inverter is, that the OPAMP output is feedbacked. So an OPAMP output is not "weak". In opposite it is very low ohmic - driving immediately as much current as possible - trying to get the desired output voltage, until current becomes limited.

Klaus
 
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The specification are in a sub µs range range, I doubt that they are related to power dissipation. IMHO primary purpose of maximum rise/fall time specifications is to guarantee proper signal edges. According to the quiescent current graphs given in the above linked 74HC user manuals, biasing inverter inputs near the logic threshold (mid supply in case of 74HC) causes considerable power dissipation but doesn't exceed the ratings.
From th Texas Instruments “ Implications of Slow or Floating CMOS inputs” app note:

“However, when switching from one state to another, the input crosses the threshold region, causing the N-channel and the P- channel to turn on simultaneously, generating a current path between VCC and GND. This current surge can be damaging, depending on the length of time that the input is in the threshold region“
 
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Hi,



Ordinary CD4xxx logic ICs use tiny low current Mosfets. 74HCxxxx ICs produce much higher current.
The datasheet of a CD4069 inverter shows a typical "shoot-through" current of 1mA when the supply is 5V, is 4.5mA when the supply is 10V and is 11mA when the supply is 15V. Ordinary CD4069 inverters are used as linear amplifiers when they have negative feedback and have the input biased at half the supply voltage.

Thanks. Where is that specific linear amplifier graph from, please?
--- Updated ---

Hi Klaus,

I read the whole of the Nexperia app note you posted the link to yesterday (and the Slow or Floating Inputs danadakk posted), a lot of information to absorb...

Hi,

from the document given in post#6:
* the current depends on supply voltage. (quite expectable)
* it is about 200uA at 3V Vcc.

Thus at 3V the series resistance is about 15 kOhms.

****
An OPAMP ouput stage may be short circuit prove .. or not. It may be time limited or infinite. It may depend on ambient temperautre or not. The information is given in it´s datasheet.
It usually can drive some 10s of mA. Maybe cause some 100mW of dissipated power. You can feel the temperature rise.

200uA at 3V just gives 600uW of heat. Not noticable. Much less than an Opamp output stage.
Another difference between OPAMP and logic inverter is, that the OPAMP output is feedbacked. So an OPAMP output is not "weak". In opposite it is very low ohmic - driving immediately as much current as possible - trying to get the desired output voltage, until current becomes limited.

Klaus

So, in short, no. Op amp to logic was comparing apples and pears, whoops. Thank you.
 
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danadakk

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Hi,





Thanks. Where is that specific linear amplifier graph from, please?
--- Updated ---

Hi Klaus,

I read the whole of the Nexperia app note you posted the link to yesterday (and the Slow or Floating Inputs danadakk posted), a lot of information to absorb...



So, in short, no. Op amp to logic was comparing apples and pears, whoops. Thank you.
"Linear amp graph"



Many xtal oscillators were built by strapping a 1 M ohm or higher R across inverter to bias it up into linear region and
connect pi network of xtal and 2 caps and another R to make clock oscillators. Not exactly high precision low
jitter solution, but sufficed for many applications.

1618257630647.png



Regards, Dana.
 
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That's RCA artwork, Harris had not bought GE/RCA/Intersil
yet at that time.

CD4000 was exceptionally large feature size, thick (single
layer) metal and low current, making it more tolerant of
things which became "bad ideas" later....
 
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