Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The number of gate inputs to CMOS gates is usually limited to four for both sizing and delay factors.
Lets look at the simplest NOR gate (complementary logic) as an example. it is essentially 4 PMOS in series and 4 NMOS in parallel.
Now, the more transistors you have, the more capacitance they introduce, and hence the longer delay. To offset this, designers will have to increase the transistor sizes. However, when you size up the transistors , 4 PMOS in series uses up A LOT of precious chip area.
Most importantly, it will still be slow even with the sizing. Thats why designers often limit the number of gates to 3.
P.S. The NOR gates i am talking about here is in its simplest form, in practice the design is often much more complicated (for better noise handling, etc reasons. )