I can't really help you with proving whatever you're
looking to prove, but I can say that minimum average
delay is not necessarily what you care most about, in
designing a high performance digital circuit. I've spent
a lot of time tweaking logic gates' N and P widths to
get the -critical- transition where it needs to be, and
averages don't get you anywhere past the "standard"
library release - you can find another chunk of speed
if you're willing to "step off the grid".