cmos circuits: p/n ratio for minimum average delay pleas help

[abdullah.jar]

Hi everybody.
im new here and i hope i can get help
my problem is how to prove that the best P/N ratio for minimum avearge delay is √(µ)
i proved that for inverter but i cant for NOR2 or NAND2 any help pleas showing solution stips
thank you
ps: what section in this forum for vlsi
:--!:

 

[dick_freebird]

I can't really help you with proving whatever you're
looking to prove, but I can say that minimum average
delay is not necessarily what you care most about, in
designing a high performance digital circuit. I've spent
a lot of time tweaking logic gates' N and P widths to
get the -critical- transition where it needs to be, and
averages don't get you anywhere past the "standard"
library release - you can find another chunk of speed
if you're willing to "step off the grid".