Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

cmos circuits: p/n ratio for minimum average delay pleas help

Status
Not open for further replies.

abdullah.jar

Newbie level 3
Joined
Dec 5, 2012
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,296
Hi everybody.
im new here and i hope i can get help
my problem is how to prove that the best P/N ratio for minimum avearge delay is √(µ)
i proved that for inverter but i cant for NOR2 or NAND2 any help pleas showing solution stips
thank you
ps: what section in this forum for vlsi
:-:)-:)!:
 

dick_freebird

Advanced Member level 5
Joined
Mar 4, 2008
Messages
7,048
Helped
2,058
Reputation
4,120
Reaction score
1,906
Trophy points
1,393
Location
USA
Activity points
56,502
I can't really help you with proving whatever you're
looking to prove, but I can say that minimum average
delay is not necessarily what you care most about, in
designing a high performance digital circuit. I've spent
a lot of time tweaking logic gates' N and P widths to
get the -critical- transition where it needs to be, and
averages don't get you anywhere past the "standard"
library release - you can find another chunk of speed
if you're willing to "step off the grid".
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top