clock tree synthesis

Thread starter manikanta.9332
Start date Feb 28, 2013

Status: Not open for further replies.

Feb 28, 2013

manikanta.9332

Member level 3

Hai all,

At cts stage we are adding clock buffers then we have may have a chance of congestion then how we can face that problem?

and by adding that buffers we have any Power problems? how can over come that problems?

Thanks...

Status: Not open for further replies.

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clock tree synthesis

manikanta.9332

Member level 3

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