Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

clock tree synthesis

Status
Not open for further replies.

manikanta.9332

Member level 3
Joined
Mar 29, 2012
Messages
62
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
Banglore
Activity points
1,614
Hai all,


At cts stage we are adding clock buffers then we have may have a chance of congestion then how we can face that problem?

and by adding that buffers we have any Power problems? how can over come that problems?

Thanks...
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top