Clock recovery with FPGA

[Sink0]

Hi, what whoudl be the best way to perform clock recovery with a low-end FPGA as a cyclone II or I or a Spartan III for a signal with clock ranging from 50Mhz to 150Mhz? Thank you

 

[allsey87]

Hey Sink0,

you need to use the PLL circuity inside the FPGA. unfortunately I can't tell you much more than this as I haven't gone down this path before.

Check out the documentation on the Xilinx website for the spartan 3, hopefully there would be some reference designs there to get you started: Spartan-3A

 

[sameh_yassin99]

Hello there,
I once did this job before. But the system I worked on with a mixed system. We implemented a phase locked loop as follows:
We needed to recover a 512kbit/sec clock, we had VCO chip and LPF out of the spartan3e chip. The phase detector and divider were implemented inside the FPGA.
Please note that for recovering 512kbit/sec clock we needed 8 or 16MHz VCO so that after division we can compare the phases between the incoming reference clock and the local VCO clock.
Therfore, your clock speed up to 150 MHZ needs special treating cause I dun think you can get a VCO up to 150 * 8 MHZ.
I highly recommend that you read xilinx application note xapp868.pdf by Paolo Novellini and Giovanni Guasti. The authors shows that Low data rates (less than 10 Mb/s) can be recovered by fully digital PLLs.

regards,
S. Yassin

 

[Sink0]

Thank you for the replys. I wil take a look at that document.

Just a question. Is it possible to oversample the incoming data with a clocl on the rising and falling edge, and using 2 clocks shifted by 90 degrees? That way i would have a sampling rate 4 time faster than my clock. With a 200Mhz clock i would have enough sampling speed for my application. Is it possible?

Any other sugestion or coment?

Thank you!

 

[permute]

Possibly, you can use the DCM/PLL to get a faster clock, and you can use the SERDES blocks to aid in oversampling the inputs. you can also use regular DDR inputs, but you'll still benefit from reducing clock rate in the actual design.