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clarification on I2C scl clock

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altair_06

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Hi friends,

I need a clarification on I2C scl clock.

When I2C device acts as slave will it need any internal refference clock or input scl clock alone is sufficient to sample the data ?

1.since I2C master has the capability of controlling the scl line (pull up the scl line)

2.onother case, slave is capable of pulling down scl line when it driving data Ack in that case it need a reference time period/clock so that time it can pull down the scl line for that perilod.

3. For above two cases when developing BFM's how do we take care of clock signals.

friends u can come up with what ever the your ideas

Thanks for your time
 

hi altair_06,

Slave can only drive SDA to low when it is busy, it can't make a response(send ACK).
Since the speed of I2C is too slow, we use a internal clock to sample the SCL and SDA signal to
detect the start/stop condition and also to sample the data from SDA.

Sincerely,
Jarod
 

altair_06 said:
Hi friends,

I need a clarification on I2C scl clock.

When I2C device acts as slave will it need any internal refference clock or input scl clock alone is sufficient to sample the data ?

1.since I2C master has the capability of controlling the scl line (pull up the scl line)

2.onother case, slave is capable of pulling down scl line when it driving data Ack in that case it need a reference time period/clock so that time it can pull down the scl line for that perilod.

3. For above two cases when developing BFM's how do we take care of clock signals.

friends u can come up with what ever the your ideas

Thanks for your time

The input scl clock alone is sufficient to sample the data. All the play of the data depends mainly on the SCL
As jarodz says, the slave pulls down the SCL line and it will so until it has finishd the task it made the master wait or we can employ a time-out clock to relieve the SCL.
 

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