kevinrose
Newbie level 4
Hi
i have been developing Verilog code for a design.I need to do chip level power analysis and chip level area consumption has to be found out for my design.Cadence has been suggested for power analysis .However,we have Tanner EDA.Can the developed synthesized code be given to the Tanner EDA tool and can power analysis be done and can area be estimated.This is quite urgent..
kindly reply..
regards
A.Vino
i have been developing Verilog code for a design.I need to do chip level power analysis and chip level area consumption has to be found out for my design.Cadence has been suggested for power analysis .However,we have Tanner EDA.Can the developed synthesized code be given to the Tanner EDA tool and can power analysis be done and can area be estimated.This is quite urgent..
kindly reply..
regards
A.Vino