Chip level power analysis

[kevinrose]

Hi
i have been developing Verilog code for a design.I need to do chip level power analysis and chip level area consumption has to be found out for my design.Cadence has been suggested for power analysis .However,we have Tanner EDA.Can the developed synthesized code be given to the Tanner EDA tool and can power analysis be done and can area be estimated.This is quite urgent..

kindly reply..
regards
A.Vino

 

[Adam.Yakuvitz]

I think the initial suggestion of Cadence would be better. They are much more ahead in the Low Power Chip Design game than any of the other EDA vendors. Recommendation would be to use . .
- RTL Compiler for RTL level Power Analysis (if you have complete Verilog or VHDL code)
- NC-Sim for Low Power Simulation and RTL Compiler for Power Profiling
- VoltageStorm or Encounter Power Systems (EPS) for IR-Drop and Voltage Drop analysis

-- adam

 

[kevinrose]

hi..
thanks for the immediate reply. Could u please tell me whether NC-Sim or RTL Compiler is a freeware.If so, could u pls tell me the website from where it could be downloaded.

Thank u
regards
A.Vino

 

[rsewal]

I was an RTL Compiler Core Comp Technical Leader at Cadence. The tool is NOT free. In fact, it is > $80,000. No freeware. If you want a free solution then expect poor results. Anyway, for RTL power you should use Sequence Design (now Apache) PowerTheater. Power at RTL will not be accurate. It is relatively accurate (20% to gates). Atrenta also has an RTL power solution called SpyGlass Power.

I have worked in RTL Power Analysis for years and the preparation of the simulation for power is very important. Simulation for verification may be terribly skewed and not reflect what the chip sees when plugged in the final application so the power numbers are unreal.

-Rajat Sewal

 

[kevinrose]

hi
thank u for replying.
Can a PSpice file be given as input to LTSPICE ..If not how to do the conversion.
pls excuse iam quite new to it.

regards
A.vino

 

[rsewal]

PSPICE is a PC board level simulator that uses IBIS models. LTSPICE should also read IBIS models. So the spice deck should be compatible. I actually represent Legend Design (I founded EDATechForce which represents Legend Design), that makes an IBIS based simulator so I can find out for you about LTSPICE.

 

[jiancongwoo]

Hi Kevinrose,
if you want analysis power after PR, the best tool to use is Redhawk, this tool bases on spice information to perform power analysis, this is much more better than EPS.
if you just want to analysis power @ netlist level, I think primepower will meet you requirments.