1-How many clock gating of this type do you have in your design?
There are about 20 this type cells. But only the one who's CK connected to PAD's input pin caused power consumption.
2- So the 1-2mA is only leakage power, as you indicate when CLK is high, the clock edge has no impact on the power?
Yes, the clock edge does has no impact on the power。 And I find another thing : when E is set to low(E is a internal point in chip, but I can assure it is low throw special stimultiaon) the power is nomal again. That is to say, the problem is the latch cannot hold a "High" state normally! I suspect the High state is acturally not a high, but is a midstate.
Another thing : not all of the chip have such problems, about 1/20 chips are OK.