Chip failure cause by clockgating cell

[orinoflow]

hi，every body！
I have had a lot of time on this question, but still have no answer now.
The chip is every thing ok but power consumption. By EMMI, we find the point cause the power consumption is on a clockgating cell.

And I find that only when CK is high will power consumption occur(about 1 or 2 mA, each chip is different), when CK is low the power is nomal.
CK is connected to a Digtal PAD's input pin directly.
the chip has only one power domain。
thanks!

 

[rahul.achates]

What is the fan out and loading on that inverter ? May be high loading increasing power consumption ..

 

[orinoflow]

fanout of the gating cell only have 5 flipflops. and it is a 16X cell, fanout ablility should be ok.

What is the fan out and loading on that inverter ? May be high loading increasing power consumption ..

 

[rca]

1-How many clock gating of this type do you have in your design?
2- So the 1-2mA is only leakage power, as you indicate when CLK is high, the clock edge has no impact on the power?

 

[orinoflow]

1-How many clock gating of this type do you have in your design?
There are about 20 this type cells. But only the one who's CK connected to PAD's input pin caused power consumption.

2- So the 1-2mA is only leakage power, as you indicate when CLK is high, the clock edge has no impact on the power?
Yes, the clock edge does has no impact on the power。 And I find another thing : when E is set to low（E is a internal point in chip, but I can assure it is low throw special stimultiaon) the power is nomal again. That is to say, the problem is the latch cannot hold a "High" state normally! I suspect the High state is acturally not a high, but is a midstate.

Another thing : not all of the chip have such problems, about 1/20 chips are OK.