Characterizing timing of silicon for datasheets

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jelydonut

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I have reciently recieved finished silicon and am currently trying to get timing for the datasheet. Currently how I am doing it is to capture waveforms on a logic analyser and compare them to the SDF timing in simulation. If the same, then I will use the simulation for generating the timing values.

Is this a proper way of doing this, or is there a better/easier way?

I've never seen any docs or anything on this step and am unsure if this is the proper way.

Any suggestions are appriciated.

Thanks!

jelydonut
 

first capture all timings with PrimeTime by using Final post-layout SDF. once all timings are captured, then verify all timings using the silicon validation on board by capturing waveforms on oscilloscope (not logic analyzer).

by comparing both, take the worst case ones and make a datasheet.
 

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