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Cascoding the two stage folded class AB ampliifer

Junus2012

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Dear friends,

this is one of the most popular ampliifer circuit which I am in love with it :)

I have a question about adding cascoding transistors down to MP5, MP6 and up to MN3, MN4 for the purpose of boosting the gain. This procedure I have seen with OTA same type circuit but without the class AB driver stage, so I am not sure about the consequence of doing it with this circuit.

In general, adding cascoding transistors consuming from supply headrom, however, since we have here two stage ampliifer the signal doesnt require to fully swing in the range since the driver stage provide us with gain as well

I am looking forward for your reply

Best Regards

foldedab.jpg
 

Dominik Przyborowski

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Available headrom for you current sources is the vgs of output transistors and/or vgs of diodes on the rails. The minimum value of vds for 3 mosftes is ca 450mV (if they are in weak inversion), so it is feasible to use double cascode current sources in the first stage.
The question is for what reason?
Depending on process, it might result with 80-140dB of open loop gain (and more often higher number than lower). As long as you don't need 20+bits accuracy (usually achievable in different way) boosting gain here is nothing more as asking for troubles (sensitivity on everything, potential negative resistance seen from supply, etc.)
 

Junus2012

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Dear Dominik

Thank you for your reply

you are right, i tried that and i found troubles in stability that forced me to reduce my GBW using larger capacitor, also when i increase the biasing current of my ampliifer then those cascoded transistor goes in to triode region,

my design without cascode has a gain of 105 dB under nominal condition but when i run montecarlo or worst case corners i see it can drop to 80 dB that is why i am thinking to boost it to compensate for this drop

what about three stage amplfier ? what do you think of it
 

Dominik Przyborowski

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1. Cascodes biased properly never goes into triode.
2. 20dB gain drop in MC is a lot - i suspect lack of balance between transistors. In this guy, at least MN1, MN2, MN8 and MN9 has to be matched (however, full balance is impossible due to huge V_DS mismatch).
3. As long as opamp is unloaded (no DC current is drawn), gain is set to minimum. In quiescent conditions, floating current sources are balanced and output of first stage seen low impedance of MN6 and MP8 sources. With high current drawn from output, current is flowing through one of the mosfet in floating current source, changing impedance from 1/gm into double cascode from one side (effective impedance is shunt equivalent of single and double cascode). So, you should expect at least 20dB higher gain for large output current than for quiescent case.
4. 3 stage OPAMP is tricky. Usually it has sense if capacitive load is very high (like in LED displays), in order of nF and UGF is only a few MHz.
Pennisi and Palumbo spend half their life fighting with them.

I really don't understand why you need more open loop gain.
If you already has more than 80dB (10kV/V) it is equivalent to 13 bits, which is corresponding to dynamic range with no more than 400µVrms of noises for 3.3V swing.
Moreover, usually we need a gain for signal, not DC.
 

Junus2012

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Dear Dominik,

I am very grateful to you for your reply and help,

you have pointed on many importnat points, so I will try to cover it one by one to make good use of it

You have mentioned that a well biased cascoded devices will not go in to triode, I would say that is true in case if they have enough VDS voltage to satisfy the saturation condition, in my case as I have told you the cascoded device was working fine in the saturation region but when I increased the biasing current and hence the output current of the amplifier increased that led to fail to put it in the saturation region.

I have attached you the second stage of my ampliifer with the cascoded transistor, I would please ask for your help to suggest me a biasing scheme for the cascoded device (labeled as Vbiasx and Vbiasy)so it will not go into triode region,

in my case I am assuming that cascoded transistor needs in the ideal case a biasing voltage that is = 3Von+Vth,

Thank you in advance

Best Regards circuitcascoded.PNG
 

Dominik Przyborowski

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- Hi, would you go to the party on which is 10 liters of vodka?
- hmm, for how many people?
That's all. Keep current density constant.

I do not see clearly, whether mosfets connected to rails are current sources or some of them should work in linear (triode CMFB?). I would assume, all should work in pentode. Also, I suppose you are still playing with old AMS C35? (BTW, I heard rumors is it going to be closed?)

By biasing all FETs close to strong inversion (for speed and matching), lets say IC=5, and with reasonable channel length for example 0.5µm, the dimensions of these guys should be: 3.5µm/0.5µm for NFET per 10µA current and 10µm/0.5µm for PFET per 10µA. For different current, scale NF or M in respect to current ratio.
Such biased transistors might has ca 0.65V Vgs at room temp (NMOS) varied across temp range -40°C - 125°C between ≈0.53V and ≈0.83V.
Vdsat of above mosfets will be ca 200mV at room temp and varies between 160mV(-40°C) and 260mV(125°C).

So, for single cascode there is 125mV/mosfet of VDS margin (room temp) and 100mV (-40°C) or 150mV (125°C).
For double cascode, there is only 50mV of VDS margin for all 3 mosfets, so they should be biased then deeper in moderate inversion (i.e. IC=1 means all widths 5× higher for the same current, but 65mV lower Vdsat). However, cascode compensation scheme may needs high enough ft of cascodes and might be tricky for slower transistors (ft~IC).

How to bias?
As every MOSFET, bias them by current (yes, MOSFET's operating point is defined by it current, not by a gate voltage).

Simple high-swing cascode (whatever scheme) is enough. Personally, I am a fan of Sooch, with this ≈1/3 MOSFET in triode as level shifter (cascode transistors acts as gate followers, copying VDS for all current sources). You will need to check behavior vs temperature (depending to you reference current - whether it is PTAT/CTAT or fixed - it might be different), to ensure enough Vds for current sources. The only important thing is to keep fixed current density and use unit transistors (play only with NF or M in respect to currents ratio).
 

Junus2012

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Dear Dominik,

I dont know how to thank you for your great efforts in explaining the things to me, you explain and make the things clear much more clear than I talk to my supervisor.

You talked about many principles which I am poor in it, and I will focus in every statement you have mentioned just after finishing with this so topics will not be mixed

Dear Dominik,

I usually do as you already said when I bias mirror, means always I keep current densities are equal then by the gate voltage I can bias the transistirs for example near to the saturation region or keeping safety margin for the PVT change.

What I have did rightr now, I simulaetd only the NMOS part of the output circuit from the circuit shown before, and in my design the CMFBare working in the saturation region, attached is the equivelant circuit, also I used the sooch biasing princible, the two current sources you see in the output is to simulate the two currents coming from PMOS differential pair, similarly the two voltage sources in the output is to simulate the drop voltage in the upper part of the amplifier circuit
for the sooch biasing I dont go usually to devide /3, I prefer to go more to be more sure about the saturation region
the equievelant circuit is working perfectly with the same currents simulated as exactly as it is in the ampliifer circuit,

However, once I do the same for the amplifier, it work fine but with less currents, mean to say in the equivelant circuit it was working with I = 120 µA but in the ampliifer works untill 50 µA before

transistors goes in triode region.

sooch_biasing.jpg

Thank you very much once again
Best Regards
 

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Dominik Przyborowski

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I see a problem in your biasing scheme. However, I will not show you what is wrong (sorry, I am too lazy).
For double cascode guy, I would simply go for attached scheme (3 branches for biasing the double cascode current source, part of folded cascode amp uses this structure with floating current source and output nfet):
sooch_double_cascode.png
What is important here. All mosfets has the same unit dimensions. The only parameter which is scaled is M factor (×2 means M=2) or number of devices in stack (÷2 means are two in stack - shorted gates and one placed on the second, etc.). This is intentional, due to non-equivalent behavior of single FET with doubled length in comparison to two in stack. Current ratios are arbitrary, just for example. If everything is done properly, currents are nicely ratio-ed, respect voltages are the same. The only discrepancy is V_GO voltage which might be a bit lower than V_B1 and output current which will be higher. Such discrepancy is related to V_DS mismatch between current sources (strangled by cascodes), single diode for bias output stage and output voltage itself. As I recall correctly, this technology has 10% increase in drain current for additional 1V in V_DS, for MOSFET with 0.5µm channel length. So, if VDS of output guy is around 1.65V (half of nominal supply), it is 1V higher than VDS of biasing diode, so it ID is not 16× but 17.6×Ib. And, VGO might be lower for several mV than VB1.

And last but not least - if you want change current in amplifier, change transistor sizes also. Keep current density constant. This is one of the most important rules in analog design.
 

Junus2012

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Thank you very much Domink for your nice answer,
I will soon simulate you scheme and compare it to mine which you told it has a problem,

in my scheme I was biaing (let say ideally ) as Vbias1 = Vov+Vth
Vbias2 = 2 Vov+Vth
Vbias3 = 3 Vov+ Vth

That was my ideal assumption that if successflly put every transistor at the edge of saturation region with VDS(sat) = Vov, so for three transistors Vomin=Vov1+Vov2+Vov3 and supposing current densities are equal so Vov1 =Vov2 =Vov3 = Vov that leads to Vomin = 3 Vov...... my biasing scheme worked as I said when I simulated it as a mirror but failed in the ampliifer, that is why I would try your scheme then informing you.

I forgot to tell you that AMS is going to close,

Thank you Dominik,
Best Regards
 

Dominik Przyborowski

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If separated circuit works, but fails in opamp it simply means, your output stage biasing kills all. Make it matched to current source.
 

Junus2012

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Dear Dominik

Hope you are fine after my posts :)


I have tried your biasing scheme, it is also working fine when I bias a current mirror with equivalent to the amplifier circuit as I have done before, circuit is working perfectly (althaugh I don't know about the expression equation for all the three vbias volategs in your scheme and in the same time feeling ashy to ask you for it :) )

However, it also not working when I bias the amplifier circuit,

bak to one of your replies when you mentioned about sizing, I have doubled the transistor sizes and it is now working, which explain as I expected before the source of the error emphasized by your last reply to investigate the amplifier circuit, it means the source of the error was not enough voltage for the cascoded devices (VDS) to put them in the saturation region when I increased the size the Vov is decreased so the available VDS was sufficient to put them in saturation.

I am not closing this topic now because there are other information you stated which I want to cover as well, but I want to confirm that after your help the circuit is working.

Thank you very much

- - - Updated - - -

By the way,

Althaugh the circuit is working now, but at the temperature border fail with the process corner,

So I would say, it is working as fine as in typical condition, otherwise transistor size should be huge in order to reduce the VDS(sat), right now I reached PMOS W=240 µm for the upper transistors then 120 µm then 60 µm for the biasing class AB, all with L= 1µm and I think it is bnig values when I compare it to design from literature, right ?
 

Dominik Przyborowski

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Myself said:
By biasing all FETs close to strong inversion (for speed and matching), lets say IC=5, and with reasonable channel length for example 0.5µm, the dimensions of these guys should be: 3.5µm/0.5µm for NFET per 10µA current and 10µm/0.5µm for PFET per 10µA. For different current, scale NF or M in respect to current ratio.
Such biased transistors might has ca 0.65V Vgs at room temp (NMOS) varied across temp range -40°C - 125°C between ≈0.53V and ≈0.83V.
Vdsat of above mosfets will be ca 200mV at room temp and varies between 160mV(-40°C) and 260mV(125°C).

So, for single cascode there is 125mV/mosfet of VDS margin (room temp) and 100mV (-40°C) or 150mV (125°C).
For double cascode, there is only 50mV of VDS margin for all 3 mosfets, so they should be biased then deeper in moderate inversion (i.e. IC=1 means all widths 5× higher for the same current, but 65mV lower Vdsat).
I told you, it might be hard. Above consideration were taken for "typical" corner. Fast transistors might be strangled by output stage biasing.
There are couple of solutions:
1. forget about double cascode (IMO preferred solution - in 99% cases simpler means better)
2. use gain boosting with OTA
3. boost headroom for current source, by simply use of two diodes in floating current source biasing and then source follower as a level shiftier (back to 1VGS at the gate of output guy). This solution need two more branches and decrease output current capability (avoid fully open of output fets - VDD-VGSQ is max gate voltage). Probably more fun then it is worth it.

Junus2012 said:
I reached PMOS W=240 µm for the upper transistors then 120 µm then 60 µm for the biasing class AB, all with L= 1µm and I think it is bnig values when I compare it to design from literature, right ?
There are no big or small but optimal or not sizes.
In PASTTREC chip (also 0.35µm) I have used 4400µm wide NFET because for given bias condition was optimum for noise/bandwidth trade-off. LDOs can have huge passfets - made in 130nm VREG013 chip - LDO for ATLAS strip detector readout, has passfet wide on 15mm. I have seen really huge MOSFETs in powering ASICs (visible by bare eye with area in order of mm²)

The most important is (again) current density. Every CMOS process can be normalized to unit-less model, describing transistor operation. And this behavior is well fit for devices in 10µm, 1.2µm process and 22nm as well, which are (or more precisely pretend to be) completely different. So, only after "normalization" of transistor size to it operating point is possible to justify it dimensions.

Junus2012 said:
althaugh I don't know about the expression equation for all the three vbias volategs in your scheme and in the same time feeling ashy to ask you for it :)
Based on compact model, this is combination of linear and inverse Lambert-W function of squared root of unit-less channel current.
So, it can be relatively simply and quickly estimated "by hand" as a difference between gate voltage (resulted from current) of MOSFET with two different sizes (W/L and W/4L).
However, I don't see good reason to wasting time for hand calculations with non-linear functions.
 

Junus2012

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Dear Dominik,

Thank you alot, after reading your last statemnt I couldnt stop myself from going to my lab regardless the corona condition, I just wanted to make use of the valuable notes you provided me.

I totally quitted the cascode connecttion idea afte rthe discussion with you and the troubles I faced with it.

Then you you adviced me to apply the boosting on the OTA, I supposed you are talking about this ampliifer (which is OTA+class AB ampliifer), so I boosted it by using simple differential single stage OTA, I used single ended booster amplifier, hence I need four boosters working with small biasing current (5 µA or less ). Result regardign gain is becoming too high (140 dB) which was good enough to satisfy my supervisor feelings.
The cost paid for this is 8 pF extra to balance the added amplifier,
That brings me to your status, simpler things might work better, so I am in favour of not using these boosters, ofcourse if my supervisor agrees, but generally it is functioning.

It is interesting for me the pint 3 from your last reply, I really want to work on it, but indeed I didn't figureout how the circuit looks like, excuse my stupidity for this, but if I understand your point I have found this circuit from Huj book, he used two transistors for the floating source, but those are not diodes, he didnt explain the circuit but I think he cascoded these transistors just as we cascode any mirror or current source, by any way thoses transistor has no rule on the output gain, please see the below circuit (the cascoded floating transistors M5-M12), I am not sure if this is what you ment by using two two diodes in floating source biasing, or in your mind is different circuit.

cascoded.PNG

Other point you made clear,
some other issues I would like to address it to you after clearing this, I dont want to mix your pints, all are valuable to me

Thank you once again
Best Regards
 

Dominik Przyborowski

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When I thought about gain boosting I have simple fully-diff solution (triple pair to have CMFF instead of CMFB) like below:
sooch_boost_cascode.png

I didn't read Huijsing book (at least don't remember to seen such circuit in a book) and I have no will to analyze it.
What I stated was regarded to shift voltages by source follower and doubles the headroom. As below (the simplest and natural solution):
Monticelli_2VG.png

Of course, such solution makes headroom enough even for classic cascode, but compensation path is covering source follower, which might be current-eater because of output stage input cap and potential requirements for high bandwidth there.
 

Junus2012

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Dear Dominik,

Thank you for your answer and your effort,

Regarding the gain boosting, I have tried also to use a fully differential booster amplifier similar to the one you used but not exactly the same, as shown below, it is giving me as good result as when I used the single ended amplifier which was my last decided approach

fully_diff.PNG

I want to add one important thing with the fully differential booster, I have at the first used the same biasing circuit you proposed for it to provide the voltage for VCM, which is equivelant to the saturation voltage of the down transistors (VD1), however, I saw my design failing.... then I realized this fault in this way, if I am using single ended ampliifer booster, this biasing volatge is perfect and the VDS of the down NMOS transistors with be forced by the negative feedback to be equal to this voltage which is required for saturation,
for the fully differential booster, the output vo+ and vo- under closed loop condition (ignoring offset) are equal and both equal to VCM (assuming ampliifer has enough loop gain), now this VCM will be applied to the gate of the cascoded transistor but they need a higher biasing voltage, mean VB2 from your graph

In short, I succeed to bulid the booster amplifier with this condition
1. With single ended booster ampliifer I use VD1
2. With fully differerntial amplifier booster I used VCM (of the booster) = VB2 , not working with VD1

By either cases, an additional compensation capacitors are need to compensate the circuit for the added amplifer.
I would say here that issue of boosting gain is almost solved.

Now before I want to go to the lab to try your last proposed circuit, I would like to ask you please about the advantagues of including the level shifter scheme ?

Thank you very much once again
Best Regards
 

Dominik Przyborowski

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These FD-OTAs are completely different - simply check gain from CM input to outputs.

1. With single ended booster ampliifer I use VD1
2. With fully differerntial amplifier booster I used VCM (of the booster) = VB2 , not working with VD1
So, you have done something wrong. Input devices of such boosters should be complementary, were they?

I would like to ask you please about the advantagues of including the level shifter scheme ?
Pros: almost none (higher headroom for current sources, so double cascode is possible, blabla) - but again, we back to my first post - 140dB is really ridiculous gain which asking for troubles - none book (at least, I don't remember any) mention this - risk of negative resistance seen from supply. You can have everything fine in simulations, but in silicon opamp are ringing because of it.
Cons: more current, stability, less dynamic range at output (lower current capability), potential higher non-linearity (however, class AB is already suffering on it), outputs asymmetry (due to body effect), etc.

But it is some kind of idea to solve an issue of low headroom.
 

Junus2012

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Dear Dominik,

Thaks again for the reply,

It is clear for me most of your points, well considered and aproved,

for the biasing voltage of the fully differential ampliifer, again VCM = VD1 is not functioning, however and as I told you I avoided this trouble by using single ended OTA (toal of four equivelant to two fully differential booster amplifier)

Regarding the gain = 140 dB, now I dont have it any more, this because I have reduced the channel length of the floded cascoded transistors to 0.5 µm (but keeping the same current density by reducing W proportionally) in my attempt to push the pole and zeros of those two critical transistors, results was showing me that zeros are becoming more far from the unity gain frequency which leads to less peaking for the transient or closed loop configuration.

I realized as well that althaugh cascoded or indirect compensation scheme is good in providing wider GBW for the same compensation capacitors as comparing to miller compensation scheme, but indeed the peaking is a hidden problem. My next invistegation is to use Nisted compensation scheme which should good result in between Miller and cascoded ccompensation.

If I go to your post #1, you stated that we are interested in signal gain, not in DC gain.... this is very important statement that I postponed my comment on it,
So if DC gain is not as important, why designers are working hard to improve the gain ?, or do you mean by signal gain is to increase the GBW ?

Thank you once again
 

Dominik Przyborowski

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Read carefully, please.
DC gain is needed for accuracy as it was stated. For example, in ADC design, OPAMP should has at least 6dB more gain than resolution if it is working as reference buffer and 12dB more if acting as S/H or 1st stage in pipeline (or vice versa).
Yes, UGF has importance as a parameter which can conclude various spec (many quantities might be reflected by UGF), but not always in the same way.
 

Junus2012

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Dear Dominik,

I just want to express my gratitude to you, after I carefully studied all of your comments I understood most of the thing about this circuit, without your help it was not visible to me, because you have pointed on many practical issues that I can not find in literature

Wish you all the best in your career

Best Regards
 

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Dear Dominik,

Hope your are fine

I have tried to solve your proposed biasing circuit and I posted it on the web here but still not solved

I am putting it here again

sooch2.png

what will be the difference from this one

maaaa.JPG

could you please at least refer me to the source of your proposed circuit

thank you in advance
 

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