I am having a cascode current mirror. I have ensured that current source transistor is in saturation. I was wondering, what will happen if one of the cascode transistor move to linear region? Please let me know
Cascode transistor increases the output impedance by gm*rds. If it falls into the linear region both its gm and rds will drop i.e. its gain lowers
hence lowering the output impedance and rendering an less ideal current source.
The whole point of cascode is to protect the current mirror from Vds variations & once cascode goes to linear the current source become susceptible to Vds variations -->Larger current change between the branches.
Thanks for your reply. I understood it now.
I have adjusted sizes so that for my cascodes,
Vgs > Vt and Vds> Vgs - Vt now to be in saturation
On a different note, is there any way i can find details about the dc op points that cadence prints out.
For example terms like vgt, vdss and many more are not understood
On a different note, is there any way i can find details about the dc op points that cadence prints out.
For example terms like vgt, vdss and many more are not understood
Continuing with the discussion
In a cascode current mirror I designed, the power supply is fixed ie total voltage across drain- source of both cascode and current source transistors are fixed. At the moment, I have 300mV across cascode and 320mV across current source. How can I distribute mode Vds across current source without changing power supply? Please help
To increase Vds of M1, increase L1, which means I should increase W1 to maintain W/L ratio
To decrease Vds of M4, I should decrease L4, which means I should decrease W4 to maintain W/L ratio
Over drive for cascodes are just 70mV now. Do you think I should increase this further? Because in corners I observe they swing to values as low as 40mV
To increase overdrive of cascode, i should increase its Vgs-Vt, which means increase Vgs, which means decrease W/L of the bias transistor which generates bias voltage for cascode
The whole point of cascode is to protect the current mirror from Vds variations & once cascode goes to linear the current source become susceptible to Vds variations -->Larger current change between the branches.
... To increase overdrive of cascode, i should increase its Vgs-Vt, which means increase Vgs, which means decrease W/L of the bias transistor which generates bias voltage for cascode
Thank you for the help.
I have one more question. Is there any way I can reduce the drop across the cascode transistor (Vds without changing its W/L or not touching the Vdd?
Please let me know.