Can you detect more than 2 signal edges in sensitivity list?

[sree205]

verilog question

Hi,
in the sensitivity list, is it possible to detect more than 2 signal edges ? say, if i want to have a 3 signal sensitivity list, such as posedge of a,b, and c, would it be possible?

 

[aji_vlsi]

Re: verilog question

Hi,
in the sensitivity list, is it possible to detect more than 2 signal edges ? say, if i want to have a 3 signal sensitivity list, such as posedge of a,b, and c, would it be possible?

You can do it in Verilog but not in Hardware - meaning you can't synthesize it. What are you trying to model?

Ajeetha, CVC

 

[rsjgs]

Re: verilog question

3 signal sensitivity lists are possible.. They are synthesizable in many cases.. eg. a clock, a reset and a start willl be or ed together and given the appropriate pin of a d ff.

 

[koppolu1981]

Re: verilog question

Hi,
in the sensitivity list, is it possible to detect more than 2 signal edges ? say, if i want to have a 3 signal sensitivity list, such as posedge of a,b, and c, would it be possible?

Can u pls say the requirement of checking exactly the edges.

 

[mistry.cd]

verilog question

Hi,

Mostly this coding prctice is used in verification only.
We can do this thing in verilog but it is not synthesizable.

Thanks

 

[sesl33]

Re: verilog question

Typically, when you attempt detect 2 edges, the expected result is a flip-flop. With one signal to the clock and the other to the reset pin of the flip-flop. Thus, I think that if you want to detect 3 edges, it should be synthesizable under the condition that, you have a flip-flop with asynchronous reset and asynchronous set.

i.e.
always @(posedge reset or posedge set or posedge clk) begin
if (reset)
A <= 0;
else if (set)
A <= 1;
else
A<=data_in;
end

 

[Zeng Jie-jun]

Re: verilog question

Can be synthsis, be a D-Flipflop with Async set and clr. but should notice that mix posedge and negedge may lead to the result what you didn't want.

 

[sree205]

verilog question

i tried to come up with a synthesizable code which does this, but quartus rejected it, whereas ncverilog or verilog-xl had no problems. hence the query.

i'm hoping someone would prove that this is the case with other synthesizers too.

 

[positive_edge]

Re: verilog question

It is possible to sense 3 edges in the sensitivity edges in the sentivity list.
Eg :

always@(posedge clk or posedge reset or posedge set)

I used Leanordo Spectrum Synthesizer to sythesize a i was able to synthsize as i wanted.

 

[semi]

Re: verilog question

If you use like this, it is synthesizeable :

always @(a or b or)

note : you have to define every inputs in the sensitivity list

 

[r63511]

Re: verilog question

oops. sees you're writing combinational circuit. Be cautious in level sensitive blocks.

 

[sysco_stevens]

Re: verilog question

it a bad design style,

you can use synchdronous design to replace this style.

best regards

Hi,
in the sensitivity list, is it possible to detect more than 2 signal edges ? say, if i want to have a 3 signal sensitivity list, such as posedge of a,b, and c, would it be possible?