Hi,
in the sensitivity list, is it possible to detect more than 2 signal edges ? say, if i want to have a 3 signal sensitivity list, such as posedge of a,b, and c, would it be possible?
Hi,
in the sensitivity list, is it possible to detect more than 2 signal edges ? say, if i want to have a 3 signal sensitivity list, such as posedge of a,b, and c, would it be possible?
3 signal sensitivity lists are possible.. They are synthesizable in many cases.. eg. a clock, a reset and a start willl be or ed together and given the appropriate pin of a d ff.
Hi,
in the sensitivity list, is it possible to detect more than 2 signal edges ? say, if i want to have a 3 signal sensitivity list, such as posedge of a,b, and c, would it be possible?
Typically, when you attempt detect 2 edges, the expected result is a flip-flop. With one signal to the clock and the other to the reset pin of the flip-flop. Thus, I think that if you want to detect 3 edges, it should be synthesizable under the condition that, you have a flip-flop with asynchronous reset and asynchronous set.
i.e.
always @(posedge reset or posedge set or posedge clk) begin
if (reset)
A <= 0;
else if (set)
A <= 1;
else
A<=data_in;
end
i tried to come up with a synthesizable code which does this, but quartus rejected it, whereas ncverilog or verilog-xl had no problems. hence the query.
i'm hoping someone would prove that this is the case with other synthesizers too.
you can use synchdronous design to replace this style.
best regards
sree205 said:
Hi,
in the sensitivity list, is it possible to detect more than 2 signal edges ? say, if i want to have a 3 signal sensitivity list, such as posedge of a,b, and c, would it be possible?