sureshnaidu
Member level 2
i have done post layout simulation even though there are DRC errors, but LVS is matched.is it good or bad.whether DRC errors affect circuit performance.
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let's say that the DRC error you have is metal spacing, the capacitance between those 2 nets will be a little higher...
I don't think you need to worry about those errors for post layout simulations. The error 4A.19P might increase your parasitic capacitance.