can we do post layout simulations even though there are DRC errors

[sureshnaidu]

i have done post layout simulation even though there are DRC errors, but LVS is matched.is it good or bad.whether DRC errors affect circuit performance.

 

[JoannesPaulus]

When you only have DRC errors (but LVS clean) you can run post-layout simulations. Nonetheless, the results might be incorrect: let's say that the DRC error you have is metal spacing, the capacitance between those 2 nets will be a little higher...

 

[sureshnaidu]

let's say that the DRC error you have is metal spacing, the capacitance between those 2 nets will be a little higher...

what about in this case.i have only following errors
[1406] SkewEdge:
[1] 4.1J: Minimum DIFFUSION density over 500x500um^2 area is 20%.
[1] 4A.19P: Minimum PO1 density over 1000x1000um^2 area is 15%.
[3] 4A.21M: Maximum NPLUS diffusion to nearest P+ pick-up spacing is 20um

 

[JoannesPaulus]

I don't think you need to worry about those errors for post layout simulations. The error 4A.19P might increase your parasitic capacitance.

 

[sureshnaidu]

I don't think you need to worry about those errors for post layout simulations. The error 4A.19P might increase your parasitic capacitance.

thank you. now you please see my thread "Strange problem in ASSURA RCX"