what codes cannot be synthesized in verilog
Agree with buzkiller. Anything inside the clocking statement
should be pure combie, of course in either VHDL or Verilog.
Rainboww, you infer doing combinational functions on clocking
signals. That is very bad, and in reality it shall suffer from phase shifts
and other stuff (noise, unecessary transitions).
NEVER PERFORM COMB-FUNCTIONS ON CLOCK. If you want to generate another clock from existing one, e.g. divide clock by modulo-N counter. Take registered output.
pene