Hi,
I'm very new to this. I loaded a LEF (layout exchange format) into ICC2. I want to grab all the pins and their directions, and place them on the block to create a verilog file with all the pins.
I am stuck here. Obviously if I do verilogout myDesign.v it outputs a verilog file with a top module that's empty. How do I make it output a verilog with all the pins? (called stub verilog/.vshell)
Please help! Thank you
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in icc2_lm_shell (library manager) i converted the lef design into a .ndm design. However in icc2_shell, it doesnt recognize "read_ndm" command. How do i read in the .ndm and then write verilog?
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I managed to open_lib the .ndm file. However, it is a "Frame" view, and write_verilog doesnt work with Frame view. There are "Design" and "Layout" views, how can i convert it to one of those to use with write_verilog?
Hi, I saw your post. I believe that too, however my manager is pushing to figure it out. I managed to go far enough in the tool to show him that its not possible, but he's still pushing for it. So I believe you because I tried myself, but what is there to say or show to convince him?
Thank you
however my manager is pushing to figure it out. I managed to go far enough in the tool to show him that its not possible, but he's still pushing for it.
You can't convince them, managers like that are too closed minded and clueless about even simple stuff. If you do what NotSam suggested and pretend you got ICC to do it, that will make the idiot manager happy and perhaps you'll have a good reference (though an utterly worthless reference ;-)).
Hi, I saw your post. I believe that too, however my manager is pushing to figure it out. I managed to go far enough in the tool to show him that its not possible, but he's still pushing for it. So I believe you because I tried myself, but what is there to say or show to convince him?
Thank you