Hi Vonn,
You don't need to connect your internal reset to anything to obtain a known value after power-up.
Your FFs will power-up to a known state, that is a feature of the FPGA you want to use :roll: .
Let's start from zero:
1) Don't even think about using GSR/GTS, not recommended by Xilinx in big design due to internal propagation delays of these signals, crap.
2) If you only want to initialise your FFs to a known state...write your VHDL/Verilog 'properly' and the tools (Synplify/Leo and ISE) will do the work for you.
3) To get initial values you don't need INIT stuff in your UCF (you could do that, but is double work)
4) Define a signal called something like 'areset' in your top module and whenever you describe a synchronous process, use it such as:
if areset='1' then
o1 <= '0';
o2 <= '1';
elsif rising_edge(clk) then
o1 <= a;
o2 <= b;
end if;
REMEMBER that 'areset' doesn't exist in your design, so is not connected to an external pin, it's just used to help the synthesizer to instantiate the right FF (FF reset to '0' or to '1').
When you synthesis this design your synthesizer will give you a warning about 'areset', no problem.
Build your design with ISE, open FPGA editor, go to the 2 FFs (o1 and o2) and open the CLB where they have been mapped into, for an Spartan II you should see there the INIT value you assigned during the 'if areset= '1' then'.
That always works, you always get the value you want in your pins/internal FFs after power-up. If you want to reset you FFs during normal operation you'll have to use an external signal (no DONE because it's assertes just after power-up
Regards,
-maestor