Can I use the Done signal in FPGA to reset my design

[Vonn]

fpga done signal

Iam using Sparatn II 200 connected to XC18V02
I have founded that the programing of the FPGA takes a long time so that I lost my master reset ...
The question is : Can I use the done signal internally to reset my design ?

 

[tlp71@hotmail.com]

virtex 5 user_reset

is not so simple.
To use done you need to loopback this signal inside the FPGA, in fact Done goes high when the device is corretly configured,. Xilinx sayd that after you can drive this pin otherwise if you don't sample this signal you have a device all time reet.
Better choice i think is to use the feature Startup. Is a macro that you can instantiate in your devic.
Please refer to Xilinx Manual how to use.Bye.
G.

 

[mami_hacky]

I think that it is possible. A simple logic circuit is needed outside FPGA, for making a proper delay for done ( I think the delay can be small, not more than two or three clock cycles ) and then I think Done can be a good source for doing this. So I think you can add a simple CPLD to your board and make a good reset signal from Done.
I have not used Startup till now, but we have used Done signal as the reset source in our circuits.

 

[drwho78]

You can use the DONE signal to drive a Reset IC such as the Maxim MAX6387. The output of the MAX6387 is a 140ms delayed pulse to reset your PLD.

 

[brmadhukar]

Hi,
use GTS and GSR for initializing u'r system.
BRM

 

[Vonn]

Hi brmadhukar,
Can you explain more how to use the GTS and GSR in initializing my
design ; If you have a link to a pdf or sample code that will be better

 

[ydao]

for fpga itselft, it will be reset auto after configuration. no need of treat it by user.

 

[Vonn]

I don't think so , after configuration you must control your code by reset ( as I think ) ...
I have founded a constrain that can be used in the UCF to initialize your signals values , the format as follows

INST "signal name" INIT = value;

 

[radix]

Xilinx doesn't recommend using GSR for a global reset. Check out their link "Using Dedicated Global Set/Reset Resource" at:

**broken link removed**

Radix

 

[wufengbo]

for fpga itselft, it will be reset auto after configuration. no need of treat it by user.

Yes,I agree with you.When DONE goes high,all the user logic in FPGA has been gone into its intial value.

 

[elektrom]

This is the way to generate reset signal in FPGA after complete configuration. (See Xilinx Answer Record # 14425 for more detail)

-- generate internal reset signal
rstin <= user_reset or config_rst;

-- This is the actual reset circuit that outputs config_rst. It is a four-cycle shift register.

flop1: FDS port map (D => '0', C => clkin, Q => out1, S => '0');
flop2: FD port map (D => out1, C => clkin, Q => out2);
flop3: FD port map (D => out2, C => clkin, Q => out3);
flop4: FD port map (D => out3, C => clkin, Q => out4);

-- config_rst will be asserted for 3 clock cycles.
config_rst <= out2 or out3 or out4;

 

[Vonn]

Hi wufengbo , you said that

"When DONE goes high,all the user logic in FPGA has been gone into its intial value"

I think that will happen If you put an initial value as a constrain in the UCF

If not how you control this initial value ?

Also , Regarding what elektrom said , the Xilinx answer was directed to Virtex II family using DCM
Unfortunately my design is working with Spartan II 200

 

[wufengbo]

If you have no other globle reset in your design,I think the only way is to set INIT attribute.But if you have another globle reset in your design,the initial value is what you specified in reset condition.For example,in the following code,the initial value of 'your_signal' is HIGH.In default,all the registers value are LOW.

always @(posedge clk or negedge reset_b) begin
if (!reset_b) begin
your_signal <= 1'b1;
end
else begin
...
end
end

 

[Vonn]

The problem now is that , also the initialization constrain which is

INST "signal name" INIT = value;

is not working !!!
I don't know why ?

I have read on this site : **broken link removed**

that regarding Setting the INIT Attribute

Before you can apply the INIT attribute you must modify the Synopsys setup file, which resides in:

$XILINX/synopsys/examples/template.synopsys_dc.setup.

Change the following line in that file.

edifout_write_properties_list = “instance_number \
pad_location part”
The new line, after the changes, appears as follows.

edifout_write_properties_list = “instance_number \
pad_location part” “INIT”

I can't find this location ; as Iam using ISE 6.1.03
and when I searched in xilinx folder I couldn't find similar file ?

any body know how to solve this problem ? any body did it practicaly ?

 

[maestor]

Hi Vonn,

You don't need to connect your internal reset to anything to obtain a known value after power-up.

Your FFs will power-up to a known state, that is a feature of the FPGA you want to use :roll: .

Let's start from zero:

1) Don't even think about using GSR/GTS, not recommended by Xilinx in big design due to internal propagation delays of these signals, crap.
2) If you only want to initialise your FFs to a known state...write your VHDL/Verilog 'properly' and the tools (Synplify/Leo and ISE) will do the work for you.
3) To get initial values you don't need INIT stuff in your UCF (you could do that, but is double work)
4) Define a signal called something like 'areset' in your top module and whenever you describe a synchronous process, use it such as:

if areset='1' then
o1 <= '0';
o2 <= '1';
elsif rising_edge(clk) then
o1 <= a;
o2 <= b;
end if;



REMEMBER that 'areset' doesn't exist in your design, so is not connected to an external pin, it's just used to help the synthesizer to instantiate the right FF (FF reset to '0' or to '1').

When you synthesis this design your synthesizer will give you a warning about 'areset', no problem.

Build your design with ISE, open FPGA editor, go to the 2 FFs (o1 and o2) and open the CLB where they have been mapped into, for an Spartan II you should see there the INIT value you assigned during the 'if areset= '1' then'.

That always works, you always get the value you want in your pins/internal FFs after power-up. If you want to reset you FFs during normal operation you'll have to use an external signal (no DONE because it's assertes just after power-up

Regards,

-maestor

 

[Vonn]

This is a logic solution but the problem is that when I tried to do it the synthizer gives me around 200 warning and removes many signals from my design ; finally the mapping faulted to complete :?:

No to conclude :

The Problem is : I need to initial the registers in my design by an initial value when power up

I tried the GSR and the instantiationof STARTUP_SPARTAN2 component
result : Failed
I tried to use the way maestor mentioned
result : Implementation failed

Suggested solution :
Is to use the constrain in the UCF to initialize your signals values

Problem : I don't know why doesn't work ? may be it needs setting or some thing else ?

Tool used : ISE6.1

Waiting for your comments !

 

[ydao]

In fact, Xilinx's new method is ROC and TOC.
ROC : reset on configuration.
TOC : Tri-State on configuration.

 

[maestor]

Hi,

I think the ROC and TOC modules are behavioural models, so your synthesizer will optimise them away.

Sorry Vonn, have u simulated your design at all?

If so, how do u genenerate your behavioural 'rst'? You could use a ROC component to generate you 'rst' and see if your testbench still passes.

You could also post the warnings you get in your synthesis step...so we can help to isolate the problem...

Are u using XST as your Synthesis tool, because is really crap, even in 6.1 still lacks of a lot of things that are available in Synpl!fy or Prec!sion, so I would suggest using another Synthesis tool to see what happens...

Let us know how are u getting on...

-maestor

 

[ydao]

I you have studied the docs from Xilinx, you will find how roc and toc take effect. For registers, the p&r tools will recog the reset state and write such info when generating the bit files. You need not to treat it youself, but you must use the reset style that synthesis and implement tools could recog.

 

[maestor]

What I meant with the ROC/TOC components is that... during synthesis and implementation, this reset signal will use the dedicated global three-state network and will not use local routing resources as X!linx would say. :roll:

But the ROC/TOC is not something you can see in the FPGA (you can't find it in FPGA Editor), it just helps the designer to simulate the design and force him/her to write an HDL code that the Synthesizer will understand and therefore map that 'reset' line to the dedicated logic of the chip.

-maestor