Can I use a CC for RF Impedance matching?

You can do most simulations with LTspice as well, probably slightly less comfortable. RF transistor SPICE models, e.g. BFR93 can be imported.

aht2000 said:

As a freelance, no student, I have no access or way for even trial versions of ADS or Microwave office to run similar RF simulation. I am mainly using LT Spice but obviously not an RF oriented simulator.

Any recommended free or reasonably priced real RF simulation package?

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You can do almost everything which ADS does..

AMS012 said:

The BJT with its Cbe and C2 (emitter cap to gnd) can potentially give negative resistance looking from the base terminal. In fact, it is one of the types of of negative resistance circuits which is built for designing oscillators. Just using a high enough value for C2 (like few nF of cap or even higher if possible) should avoid oscillations or negative resistance.

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I followed your proposal, and replaced the C2 with 10nf, and as you advised, the negative resistance disappeared. Of course the input impedance dropped to 400ohm, so no more 1500 ohm input impedance but as I understood from a recent response, I need to replace the transistor with a real RF one, which I did and as per LTSpice got me back the 1500 ohm input impedance that I am looking for.

FvM said:

You can do most simulations with LTspice as well, probably slightly less comfortable. RF transistor SPICE models, e.g. BFR93 can be imported.

Click to expand...

vfone said:

Looks like is about Miller effect, due to improper transistor used (2N3904).
Placing the same schematic from post #4 in a real RF simulator, and using an RF transistor (BFR93), I got decent S11 (at 1.5k) and S22 (at 330 ohms). Stability K factor is above 1 for a wide frequency range.
Adjusting the DC bias of the transistor gets even better results.

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I did with a BFP420 (attached its .asy and .lib), and the LTSpice results look promising. Please see attached Z11 and Z22. However, looking at S21, the gain peak is at 50MHz, I tried to increase C2 to move the peak to the left, it does but it gets flatter, and at C2=10nf, the input impedance is reducing (expected). Is there a way to maximize the gain at 10.7MHz, and still keep the Z11 and Z22 unchanged at the same frequency?

I know that this transistor has gain far beyond this frequency range, and I am happy with the bell shape curve for S21 as to avoid unwanted oscillation at high frequency, but I am not able to identify which part of the circuit is responsible for taking the gain down above 50MHz??

The circuit has high-pass behaviour by C2 and low-pass behaviour by miller capacitance in combination with the source impedance. If you want higher gain at lower frequencies, you need to increase C2. As previously discussed, large signal behaviour of the receiver is degraded by having too much gain before the IF filter.