Can i store 128X128 X 10 Images

[abdkhan]

Hi Every one ,

I'm building and image processor , I want to store ten 128 X 128 images (8 bits per pixel)
in the Memory of a verilog code(i.e. Processor)
Let me ask it in another way


I have images sized 128 X 128

Bits per pixel are 8

need to store 10 images
total sized required will be 128 X 128 X 8 X 10 = 1310720

can is declare this much memory on any FPGA in the following way ?
considering all pixel in a row orientation

Verilog :

reg [1:160000] mem[1:8];​

VHDL:

type memory_array is array (0 to 160000) of std_logic_vector(7 downto 0);
​

Can FPGA store this much amount in actual ? (any FPGA)


Regards

 

[phobos1]

u want a 160kbytes of memory to be present in block ram of fpga i dont think its availble even if it is available it will cost u more. u can try any external memory device for storing this data.

 

[abdkhan]

Dose This Statement use block memory of FPGA ??

- - - Updated - - -

I have attached some FPGA comparison XILINX, Dose This Statement use block memory of FPGA ??
http://www.xilinx.com/products/silicon-devices/fpga/index.htm

 

[TrickyDicky]

Its not as simple as creating a large array. You need to make sure the sizes and behaviours are appropriate for the chip.

 

[ads-ee]

I want to store ten 128 X 128 images (8 bits per pixel)
I have images sized 128 X 128
Bits per pixel are 8
need to store 10 images

Verilog :

reg [1:160000] mem[1:8];​

VHDL:

type memory_array is array (0 to 160000) of std_logic_vector(7 downto 0);
​

These two declarations are different. In the VHDL declaration you have an array of 160,000 bytes. In the verilog declaration you have an array of 8 160,000-bit wide words.

You declare an array of bytes in verilog as reg [7:0] mem [0:128*128-1]; FYI, 128*128 isn't 160000. You probably really want to declare each of the 10 arrays separately. You also don't want to start the array with index 1 as address 0 of the memory will be the last (rollover in the address value) address in the array. It's okay to do that if you want strange looking code that others will be criticize later. ;-)

The amount of memory if broken down to bytes would require 128*128/4096=4 BRAMs in V6 Artix 7 etc which have 36Kb rams. Altera has smaller RAMs I believe but more of them. So in those Xilinx parts you would use 40 BRAMs for the 10 arrays. This would even fit in the smallest Artix part.


Regards