can anyone help me with this problem?

[aglow_pig]

hi,everyone

1. there is a cap C1 as depicted in the attachment picture.it's connected to the gate of the NMOS M1.now,i want to know how can i get its equivalent capacitance at the output node.
2. i want to get a simulation result about f-V curve of a VCXO.how can i get it?

thx

 

[aglow_pig]

and the NMOS is worked in saturation region.

can anyone tell me how to do with this problems?

 

[eng_Semi]

for ur first question:
u can assume that at low frequencies, the drain gate parasitic capacitance will be open circuit, so u will not see C1 at the output.

But at higher frequencies, the drain gate capacitance will be short circuit, so u will see C1 at the output.

In between, u will find a combination between C1 and gate drain capacitance

Added after 1 minutes:

my assupmtion is based on C1 < Cgd

 

[aglow_pig]

in the circuit,C1>Cgd.but i still want to get the exactly equivalent capicitance at the output of c1.
now at the higher frequency as you said(like :10Mhz),does the C1 still shorted when C1>Cgd?
I think i can take the NMOS as an network about cap-res to caculate the equivalent cap.but i'm confused whether i take the vccs and gds into account.

thx for ur help!

 

[montage3000]

at last it is series of cgs and c1

 

[aglow_pig]

thx you, montage and eng_semi.
i'm a beginner of anlog ic design.i still have a little confused about this problem.

the vccs and gds are series with C1 and Cgs.so is the circuit's small signal diagram shown below right?if i get 3 equations from the node A,B,C using KCL and try to resolve it,i found it is very difficult to get the output's resistance VO/IO.can you give me some advise to resolve it?

thx a lot!