can anyone help me to write code for this circuit............

[samuel jackson]

please give me codes for thi circuit

 

[mrflibble]

You might want to google on "carry save adder verilog" or "carry save adder vhdl" depending on what you want. Also, googling "half adder" with verilog/vhdl might be useful.

 

[samuel jackson]

i have actually written code for this circuit the only problem is that i am not getting proper simulation results

 

[TrickyDicky]

what counts as "proper"
why not post the code?

 

[samuel jackson]

these are my codes

entity csadd is
Port ( a,b,CLOCK : in STD_LOGIC;
S:OUT STD_LOGIC;
cout,cin:inout std_logic);
end csadd;
architecture Behavioral of csadd is
component DFLIPFLOP is
Port ( D,CLOCK: in STD_LOGIC;
Q : out STD_LOGIC);
end component;
signal s1,cout1:std_logic;
begin
s1<=a xor b xor cin;
cout1<=(((a xor b)and cin) or (a and b));
u1FLIPFLOP port map(s1,CLOCK,s);
u2FLIPFLOP port map(cout1,CLOCK,cout);
cin<=cout;
end Behavioral;

see if there are any errors or mistakes in the algo. this ckt. is really pissing me off................

 

[mrflibble]

Why not just make a submodule for the halfadder (HA) and write out the logic exactly as in the circuit? I found this a bit hard to read, but that may well be because 1) it's late 2) I'm a verilog guy and 3) you didn't use code tags.

 

[samuel jackson]

i have tried using submodule tech. but in the rtl view it leaves one port of the two HA OPEN......
STILL THANKS FOR YOUR ASSISTANCE......

 

[TrickyDicky]

where is the DFLIPFLOP definition?
Why not just put it in the same file?

process(clock)
begin
 if rising_edge(clock) then
    cout <= cout1;
  end if;
end process;

 

[samuel jackson]

there is no problem using it either way,the problem is that i am not gettin the proper simulation results.............

 

[TrickyDicky]

where is the testbench or stimulation file?
You havent said what error you are getting.
Post the waveform.

And whats wrong with the results?

 

[samuel jackson]

dflipflop desc. Is in submodule program and it has the same coding

---------- Post added at 11:59 ---------- Previous post was at 11:57 ----------

in the simulation results it is showing red crosses.

 

[mrflibble]

dflipflop desc. Is in submodule program and it has the same coding

---------- Post added at 11:59 ---------- Previous post was at 11:57 ----------

in the simulation results it is showing red crosses.

Well, this makes it totally clear what the problem is then!

You just have to rearrange the thing with the characteristic. After that you just change the other thing and it should work! This approach will even get rid of any red crosses.

 

[TrickyDicky]

dflipflop desc. Is in submodule program and it has the same coding

---------- Post added at 11:59 ---------- Previous post was at 11:57 ----------

in the simulation results it is showing red crosses.

Sounds like a multiple driver error, or if its a bus - Uninitialised signals.

Why not help us before we can help you, and post what I asked for.

 

[mrflibble]

Sounds like a multiple driver error, or if its a bus - Uninitialised signals.

Uninitialized signals would be my guess. Which is precisely why I suggested rearranging the thing with the characteristic. That always solves it for me.

One of these days I am going to post a "help us help you" thing, where I shall strive to keep the sarcasm to a personal alltime low record. Truly nothing personal for or against the OP, but it's hard to give useful help based on what little info is given. And it's not just this post, but quite a few others as well...

So samuel, please give more info like TrickyDicky asked for. It helps us help you.

As much code as you can. A testbench that we can actually run always helps. A screenshot of your own run of the testbench, plus a description of what you think is wrong with it. The people that give that sort of info generally get a useful answer a whole lot quicker.

 

[TrickyDicky]

Uninitialized signals would be my guess. Which is precisely why I suggested rearranging the thing with the characteristic. That always solves it for me.

But is it automatic?
is it systomatic?
is it hydromatic?

 

[mrflibble]

But is it automatic?
is it systomatic?
is it hydromatic?

Why, yes it is! How'd you know?

 

[samuel jackson]

https://obrazki.elektroda.pl/34_1328100828.png
these are my simulation results................

---------- Post added at 22:55 ---------- Previous post was at 22:54 ----------

https://obrazki.elektroda.pl/34_1328100828.png
these are my simulation results................

---------- Post added at 23:01 ---------- Previous post was at 22:55 ----------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY csadd1_selfcheck_beh IS
END csadd1_selfcheck_beh;

ARCHITECTURE testbench_arch OF csadd1_selfcheck_beh IS
COMPONENT csadd
PORT (
a : In std_logic;
b : In std_logic;
CLOCK : In std_logic;
S : Out std_logic;
cout : Out std_logic;
cin : InOut std_logic
);
END COMPONENT;

SIGNAL a : std_logic := '1';
SIGNAL b : std_logic := '1';
SIGNAL CLOCK : std_logic := '1';
SIGNAL S : std_logic := '0';
SIGNAL cout : std_logic := '1';
SIGNAL cin : std_logic := '0';

SHARED VARIABLE TX_ERROR : INTEGER := 0;
SHARED VARIABLE TX_OUT : LINE;

BEGIN
UUT : csadd
PORT MAP (
a => a,
b => b,
CLOCK => CLOCK,
S => S,
cout => cout,
cin => cin
);

PROCESS
PROCEDURE CHECK_S(
next_S : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (S /= next_S) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns S="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, S);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_S);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_cout(
next_cout : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (cout /= next_cout) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns cout="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, cout);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_cout);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
BEGIN
-- ------------- Current Time: 100ns
WAIT FOR 100 ns;
CLOCK <= '1';
a <= '1';
b <= '1';
cin <= '0';
CHECK_cout('1', 100);
-- -------------------------------------
-- ------------- Current Time: 150ns
WAIT FOR 50 ns;
CHECK_cout('Z', 150);
CHECK_S('X', 150);
-- -------------------------------------
-- ------------- Current Time: 200ns
WAIT FOR 50 ns;
CLOCK <= '0';
a <= '0';
b <= '0';
CHECK_cout('0', 200);
-- -------------------------------------
-- ------------- Current Time: 250ns
WAIT FOR 50 ns;
CHECK_cout('Z', 250);
-- -------------------------------------
-- ------------- Current Time: 300ns
WAIT FOR 50 ns;
CLOCK <= '1';
a <= '1';
b <= '1';
CHECK_cout('1', 300);
-- -------------------------------------
-- ------------- Current Time: 350ns
WAIT FOR 50 ns;
CHECK_cout('Z', 350);
CHECK_S('0', 350);
-- -------------------------------------
-- ------------- Current Time: 400ns
WAIT FOR 50 ns;
CLOCK <= '0';
a <= '0';
CHECK_cout('0', 400);
-- -------------------------------------
-- ------------- Current Time: 450ns
WAIT FOR 50 ns;
CHECK_cout('Z', 450);
-- -------------------------------------
-- ------------- Current Time: 500ns
WAIT FOR 50 ns;
CLOCK <= '1';
CHECK_cout('1', 500);
-- -------------------------------------
-- ------------- Current Time: 550ns
WAIT FOR 50 ns;
CHECK_cout('Z', 550);
CHECK_S('1', 550);
-- -------------------------------------
-- ------------- Current Time: 600ns
WAIT FOR 50 ns;
CLOCK <= '0';
CHECK_cout('0', 600);
-- -------------------------------------
-- ------------- Current Time: 650ns
WAIT FOR 50 ns;
CHECK_cout('Z', 650);
-- -------------------------------------
-- ------------- Current Time: 700ns
WAIT FOR 50 ns;
CHECK_cout('1', 700);
-- -------------------------------------
-- ------------- Current Time: 750ns
WAIT FOR 50 ns;
CHECK_cout('Z', 750);
-- -------------------------------------
-- ------------- Current Time: 800ns
WAIT FOR 50 ns;
CHECK_cout('0', 800);
-- -------------------------------------
-- ------------- Current Time: 850ns
WAIT FOR 50 ns;
CHECK_cout('Z', 850);
-- -------------------------------------
WAIT FOR 150 ns;

IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT, string'("No errors or warnings"));
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No problems detected."
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT,
string'(" errors found in simulation"));
ASSERT (FALSE) REPORT "Errors found during simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;

END testbench_arch;



this is the test bench.................

---------- Post added at 23:07 ---------- Previous post was at 23:01 ----------

please even check the coding that i have posted is correct for the corresponding circuit................




regards
samuel jackson

---------- Post added at 23:10 ---------- Previous post was at 23:07 ----------

please be specific on the .........."thing"...............

 

[TrickyDicky]

we're still missing the code for DFLIPFLOP.
plus you're missing clock from the timing diagram

But I notice from your testvbench code you're changing the clock when you change the inputs. Usually things only work on the rising_edge of the clock.