Calibre settings for exact matching of transistor values

[santhua]

Hi,

I have a doubt if there are any calibre settings to match transistor parameters exactly instead of matching there total widths.

Scenario 1: If my schematic has a nmos with total_width =25u, l=400n, fingers=1
m=1 and my layout has a nmos of total_width=25u, l=400n, fingers=5.

Scenario 2: If my schematic has a nmos with total_width =25u l=400n fingers=1 m=1 and my layout has 5 nmos of total_width=5u, l=400n, fingers=1 tied parllel.

In both scenarios LVS would return clean but is there a setting in such a way these can be detected.

Calibre version is 2010. PDK currently using TSMC65

Thank you.

 

[iterativeend]

Re: Calibre settings

Check your LVS rule file. There should be an option to do what you want. Depening on the fab company the option may be diff. In mine the option is "reduce parallel mos".

I have never used this option, so pls. could you reply back if it works!