soa
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Dear All,
I am using IBM130nm technology,
when I want to check LVS, there is an error in mismatch between layout and schematic.
even if I use a single nfettw from standard library (cmrf8sf), the error remains the same.
the error is in number of pins: in layout the nfettw has 4 pins for fet while in the schematic the nfettw has 6 pins
I think LVS checks just 4 pins in layouts (G D S B) and separates the NW contact as new component (subc).
I appreciate if somebody can help me.
Thanks a lot
I am using IBM130nm technology,
when I want to check LVS, there is an error in mismatch between layout and schematic.
even if I use a single nfettw from standard library (cmrf8sf), the error remains the same.
the error is in number of pins: in layout the nfettw has 4 pins for fet while in the schematic the nfettw has 6 pins
I think LVS checks just 4 pins in layouts (G D S B) and separates the NW contact as new component (subc).
I appreciate if somebody can help me.
Thanks a lot