soa
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I'll try to check this cell tomorrow on IBM PDK v1.8. Are You sure about using a correct calibre settings for LVS? On the first look it could be good...
In IBMCMOS8RF I using "multiple partpath" to making a well/substrate contacts and surrounded whole transistor with it.
* CDL Netlist updated for Extraction on: Fri Jun 28 20:12:22 CEST 2013
*.EQUIV tdndsx=diodendx
*.EQUIV ind=ind_inh
*.EQUIV inds=inds_inh
*.EQUIV indp=indp_inh
*.EQUIV bondpad=bondpad_inh
************************************************************************
* auCdl Netlist:
*
* Library Name: VARIOUS
* Top Cell Name: nfettw_lvs
* View Name: schematic
* Netlisted on: Jun 28 20:11:46 2013
************************************************************************
.INCLUDE /vlsicad/micsoft/IBM_CMOS8_V1.8_DM_vcad/IBM_PDK/cmrf8sf/V1.8.0.4DM/cdslib/cmrf8sf/subcircuit.cdl
*.EQUATION
*.SCALE MICRON
*.MEGA
.PARAM
*.GLOBAL sub!
*.PIN sub!
************************************************************************
* Library Name: VARIOUS
* Cell Name: nfettw_lvs
* View Name: schematic
************************************************************************
.SUBCKT nfettw_lvs IN Idc VDDA VSSA
*.PININFO IN:I Idc:B VDDA:B VSSA:B
XT0 Idc IN VSSA net5 VDDA sub! nfettw m=1 l=120.0n w=4u nf=1 par=1 ngcon=2
+ mSwitch=0 idg=0 t3well=0 psp=0
XI3 VSSA net5 subc
XI0 VSSA sub! subc
.ENDS
I don't know. I know only that models for rf transistors including more things than "normal" ones.
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