Cadence: Steps for Functional verification of synthesized netlist

[chip-monk]

How does one functionally verify a netlist synthesized using the RTL Compiler? Please give steps and associated commands.

Thanks.

 

[lostinxlation]

just point to the libraries and run a simulation on the netlist.

 

[chip-monk]

Hi,

Thanks for the quick reply.

I am using VT Standard Cell Library and there is no *.v file containing all the gates such as and, inv etc used in the synthesized netlist.

So, how do I point to the library gates when I have the synthesized netlist, sdf, and *.lib file but no verilog file with all gate descriptions such and2_1 or nand etc. used in the synthesized netlist.

To be more precise, I get the errors like the following one in Cadence, when I compile the synthesized netlist, annotate the sdf file in the testbench and then use ncelab command.

and2_1 g631(.ip1 (B[8]), .ip2 (n_15), .op (c_out));
|
ncelab: *E,CUVMUR (./gen_ks_sa1.v,1817|12): instance 'test.ks_sa1_1.d9_1.a9_1.g631' of design unit 'and2_1' is unresolved in 'worklib.adder_ks9:module'.

 

[kornukhin]

You NEED verilog libraries to simulate your design. There is no other ways to simulate netlist.
Another way - to use Confornal for Formal Verification. It supports *.lib as input format.