Cadence Layout (help)

[Beardolphinaries]

After I draw the layout, check the DRC, and extractd, then can I just run simulatiion from Analog Environment and this is the post layout design, isn't it? Thanks

 

[pk3316]

You need to build a config view to specify which view you wanna simulate. If you choose schematic view, then you simulate without post layout. If you specify extracted view, you will simulate the layout effect.

 

[Beardolphinaries]

thanks a lot.
I've got another question.
In layout, can I add 'vdd!' and 'gnd!' and power supply and ground? It seems doesn't work. When I change these global to normal vdd and vdd label, it works again. What's the wrong this this?
Thanks.

 

[McSim]

In layout, can I add 'vdd!' and 'gnd!' and power supply and ground? It seems doesn't work. When I change these global to normal vdd and vdd label, it works again.

Layout pins names must be identical with schematic pin names. Otherwise, your LVS will report the error message (but you will still be able to run RCX procedure).
As I understand your problem, your layout and schematic pins names don't match.

P.S. By the way, creating config is not the only way to extracted view modeling: you can also type "av_extracted" (or other extracted view name you use) as the first position at "Switch View List" of Environment Options (Analog Design Environment window-> "Setup" menu->"Environment..."). But using of config file is much more practical as you can easily see what you currently use and change it.

 

[Beardolphinaries]

Hi, my configuration is this:

1. I have a LOGIC_INV cell, including schematic, layout, symbol and extracted view. The LVS looks ok. Than, I created an LOGIC_INV_test schematic to test this inverter. and I created the LOGIC_INV_config view as well. (Forget about the big output pin, just want to see the parasitic of wire)

After I opened the analog environment from LOGIC_INV_test schematic, I just setup the design view is 'config', the analysis is 'trans'. And there is a stimuli 'vdd!' available in Global sources, and setup it as 1.2V.

Then simulating. Got an fatal error said that 'terminals are connected together'

If I turn off the stimuli of vdd!, only the OUTPUT of schematic view is simulated. The OUTPUT_LAY of extracted view is the same as input.

I couldn't find the where the problem is. Could you help me about this? Thanks a lot.

 

[Beardolphinaries]

can anyone help me please? I really couldn't find the problem. Maybe just a very simple stupic mistake which I ignored. Thanks a lot.

 

[standup]

can you tell me how you can get the symbol of the extracted inverter_lay?Don't you check your layout with Calibre or other tools？
then,I view your question as the netlist errors.Would you like to attach the netlist extracted from the layout?
We can disscuss the questions concerning analog IC design.QQ:280325789