Hi, my configuration is this:
1. I have a LOGIC_INV cell, including schematic, layout, symbol and extracted view. The LVS looks ok. Than, I created an LOGIC_INV_test schematic to test this inverter. and I created the LOGIC_INV_config view as well. (Forget about the big output pin, just want to see the parasitic of wire)
After I opened the analog environment from LOGIC_INV_test schematic, I just setup the design view is 'config', the analysis is 'trans'. And there is a stimuli 'vdd!' available in Global sources, and setup it as 1.2V.
Then simulating. Got an fatal error said that 'terminals are connected together'
If I turn off the stimuli of vdd!, only the OUTPUT of schematic view is simulated. The OUTPUT_LAY of extracted view is the same as input.
I couldn't find the where the problem is. Could you help me about this? Thanks a lot.