Cadence introduces C-to-Silicon Compiler

[elec-eng]

cadence c2s

Cadence Design Systems, Inc. introduced C-to-Silicon Compiler, a high-level synthesis product supporting the creation and re-use of system-on-chip IP. The innovative technology in C-to-Silicon Compiler helps bridge the gap between register transfer level (RTL) models — commonly used to verify, implement, and integrate SoCs — and system-level models, usually written in C/C++ and SystemC.
C-to-Silicon Compiler is the first product delivered from a new initiative codenamed Sydney and was developed within an internal incubation group headed by Michael McNamara, vice president/general manager, C-To-Silicon Compiler. The product aims are twofold: to bridge the gap between the use of C as a design language and RTL description of the design, and to improve the silicon implementation of the design by providing a direct link between manufacturing constraints and the C description.


**broken link removed**articleID=209000061&cid=NL_edadl

 

[gliss]

c2silicon cadence

Interesting. Let's see how this does..

 

[shiv_emf]

c2silicon compiler

what are chances for this product to be sucessful ?

any updates on this ?

 

[ljxpjpjljx]

c to silicon compiler

if this tool is so powerful , we will lost job!

 

[khamitkar.ravikant]

cadence c-to-silicon compiler

is there any further documentation on this so that we can learn new and more thing like this is so good in deed

 

[korgull]

cadence c2silicon

Here is some documentation I got from Cadence when I asked about it yesterday..

 

[bright0927]

c to silicon compliler

I am afraid that digital engineers will encounter a challange

 

[skymusic]

c2s cadence

C2Silicon compiler can not optimize the size and power. The best chip is developed by best engineer

 

[bright0927]

cadence c2silicon power

C2Silicon compiler can not optimize the size and power. The best chip is developed by best engineer

but I think it is a revolution in asic design, as synthesis tool was produced many years ago. maybe rtl code generated by C2Silicon not optimized in size and power, but the efficency and productivity take much advantage, as now, no one design the asic without synthesis tool.

 

[armmips]

It is a good idea. Thanks for sharing

 

[g12tan]

The info seems very sketchy. Are there any "success" stories published?

 

[aravind]

c2s is good revolution product ..
everyone should try

 

[pmat]

Hi all,
can someone explain the way formal verification is performed using C2S?
Are there any Formal Verification tools which support this flow?
Thnx,
Pavlos