JitterJaw
Newbie level 6
Hi all,
Im trying to set voltage parameters for a vpwl source.
what I would like to do is to set the voltage to a sum of 2 other parameters that I have, IE : Voltage 1 = vdd + delta. When I try to simulate it using spectre Im getting a netlist error, any idea how it should be done ?
another question : Id like to stimulate my analog design using verilog files, is that possible can any one reference me to a good tutorial ?
thanks
Im trying to set voltage parameters for a vpwl source.
what I would like to do is to set the voltage to a sum of 2 other parameters that I have, IE : Voltage 1 = vdd + delta. When I try to simulate it using spectre Im getting a netlist error, any idea how it should be done ?
another question : Id like to stimulate my analog design using verilog files, is that possible can any one reference me to a good tutorial ?
thanks
