Caches L1 & L2 interconnect

[ivlsi]

Hi All,

Could you help me with letting know what signals are running between L1 and L2 caches? I did some search with Google, but did not find anything useful. Can somebody help?

Thank you!

 

[rca]

Well, I beleived that is the "intelligence" of this system, rarely shared or patent protected.

 

[ivlsi]

Intel published this info for their Pentium processor, I saw it on the net, but cannot find it now...
I'm attaching the interconnect schema, which I have. Could somebody let to know the meaning of the signals there?