[SOLVED] Bulk connection in CMOS Fabrication

[bio_man]

Hi All,

I remember that if I'm targeting CMOS Fabrication, rule of thumbs, bulk connection of pMOS must be connected to +VDD and bulk connection of nMOS must be connected to GND/-VSS. Is this true in all time? or as a designer you have the option to connect the bulk to higher/lower potential but not necessarily the extreme voltages in the circuit.

this came in mind, because I have a circuit with couple of floating transistors, i.e drain/source are not tied to the VDD/GND. so I was thinking if I can connect the bulk to drain/source to make Vsb=0 and avoid the body effect. I am not sure if this permissible in CMOS fabrication? BTW, if for for example bulk is connected to source in M1 and I am aware of the fact that Drain of this source should be higher the Vb or Vs to prevent forward biasing the pn junction between bulk and drain, and the opposite when connect bulk to drain.

 

[hamidmoallemi]

No , as I know this is not a fabrication rule
and the designer can can connect bulk (e.g Nwell of Pmos) to another node, but in most cases you must connect Bulk to voltage extremes

 

[AMS012]

If the process is what is called triple well process, then NMOS can have a separate pwell in which case you can connect that pwell to any potential you want. And regarding pmos, the nwell can always be connected to any potential you want.

 

[bio_man]

Thanks all for your input.