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# blocking and non blocking in verilog

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#### ASIC_intl

##### Banned
Why do we use blocking assignments for combination always statements and non blocking assignments for sequential always statements in a verilog RTL?

#### dhaval4987

##### Full Member level 3
Blocking assignments assign the value immediately, where as non blocking assignments first evaluate the value and then assigns it in the next event change- just the way sequential circuits work. They always sample the value of rising/falling edge of clock.

#### bbgil

##### Full Member level 2
Verilog supports two types of assignments within always blocks, with
subtly different behaviors.
Blocking assignment: evaluation and assignment are immediate
Nonblocking assignment: all assignments deferred until all right-hand
sides have been evaluated (end of simulation timestep)
Sometimes, both produce the same result. Sometimes, not!

#### ASIC_intl

##### Banned
dhaval

Is your comment "Blocking assignments assign the value immediately, where as non blocking assignments first evaluate the value and then assigns it in the next event change" is true for simulator? Or, is it true for synthesis tool also?

However your explanation is not clear. Can u please elaborate more? The sequential circuit always evaluates the value at clock edge. How is related to blocking assignments?

#### muni123

##### Member level 3
Sequential circuits wait for the clock edge to output a value, just as it done in the non blocking assignments where the outputs are driven at posedge or negedge of the clock.
Considering a combinational circuit there is immediate change in output with the change in any of the input, here the case we go for blocking assignments where the output is driven at the given simulation time.

However synthesis tools doesnt consider the timing delays we provide. They come out with the path delays due the combi and seq logic we have written.

Hope this answered your question.

#### ASIC_intl

##### Banned
Hi muni

Even for blocking assignments also the outputs are driven at posedge or negedge of the clock if the always contain posedge or negedge of clock.

So it is not answering the question.

Suppose u want to write RTL for a single D-flipflop. Wht should u use then, blocking or not blocking and why?

#### muni123

##### Member level 3
While going for D-Flipflop we definitely go for a non blocking assignment as the output must be available at the posedge of the D-flipflop.
secondly coming to your question..
"Even for blocking assignments also the outputs are driven at posedge or negedge of the clock if the always contain posedge or negedge of clock."

We can include the blocking assignments inside an always block along with non blocking assignments if you are including the combi logic too along with seq logic in the same always block. However this is not good coding style. Usually we go for separate always blocks for seq logic and combi logic.

#### dhaval4987

##### Full Member level 3
dhaval

Is your comment "Blocking assignments assign the value immediately, where as non blocking assignments first evaluate the value and then assigns it in the next event change" is true for simulator? Or, is it true for synthesis tool also?

However your explanation is not clear. Can u please elaborate more? The sequential circuit always evaluates the value at clock edge. How is related to blocking assignments?

With blocking assignments each statement in the same time frame is executed in sequential order within their blocks. If there is a time delay in one line then the next statement will not be executed until this delay is over. Non-Blocking assignments tackle the procedure of assigning values to variables in a totally different way. Instead of executing each statement as they are found, the right-hand side variables of all non-blocking statements are read and stored in temporary memory locations. When they have all been read, the left-hand side variables will be determined. They are non-blocking because they allow the execution of other events to occur in the block even if there are time delays set.

#### FvM

##### Super Moderator
Staff member
@ASIC_intl: I realize, that you are around at edaboard since some time and have started several HDL related discussions, which suggests, that you aren't a Verilog beginner. I guess you know, that the blocking/non-blocking topic is a series topic at edaboard and presented very detailed in Verilog textbooks. So I wonder, why you are starting thread number 101 (may be more) with this old standard question and then complain about other contributors answers.

If you don't have a text book at hand, I suggest the classical cummings paper:
https://www.edaboard.com/threads/175727/

syeda amna

### syeda amna

Points: 2
Helpful Answer Positive Rating

#### ASIC_intl

##### Banned
Fvm:
You are right, I have verilog books which clearly explain what is blocking and what is non blocking assignments. The paper you suggested may be a good paper. Let me see to it. Thanks for pointing to this paper.

I am not complaining to other contributors answer. Rather I am clarifying about what they want to say. The sole region we raise a block to share knowledge of each other, not for complain.

Do you know good paper of other topics from classical cummings papers? Please let me know.

#### ASIC_intl

##### Banned
Hi FVM

In the said document for blocking and non blocking assognments, can u please explain about the self triggering always block that is in page 7-8. It is not clear how the always block is being entered as there is no event triggering in the clock. The clock only is initialized to zero at #10. So there is no event on the clock and hence always block will not be executed. But thery are taking of execution of always block. How?

Regards

#### FvM

##### Super Moderator
Staff member
It is not clear how the always block is being entered as there is no event triggering in the clock.
I'm not sure about. May be the initial block acts as a trigger. In my opinion the self-triggering always block is rather unusual. Or as the author said "not necessarily a recommended coding style". And I wonder if it actually serves a purpose. This clk generation scheme (e.g. usable for testbenches) is suggested in the Verilog IEEE standard:
Code:
always begin
#50 a = ~a;
end

#### ASIC_int

##### Advanced Member level 4
FVM

Which clock generation scheme is suggested in Verilog IEEE standard? The one that is there in the paper and we are not able to understand?

Another question:
Does synthesis tool evaluate the always blocks one after another instead of concurrently if there are more than one always block in one module? That what we can infer from that paper from example 7 and example 8 at page 9. What do you think?

But verilog language says that the always blocks are concurrents. So they should be evaluated together by the synthesis tool and not one after another? What is your comment about this?

Regards

#### FvM

##### Super Moderator
Staff member
You are asking about Verilog for synthesis. A general remark should be kept in mind: (IEEE Std 1364-2005 §11.1)
Although the Verilog HDL is used for more than simulation, the semantics of the language are defined for simulation, and everything else is abstracted from this base definition.
Some problems relevant for simulation are meaningless in synthesis, e.g. level sensitive events in always blocks or timed assignments (like #50 a = ~a. Both are simply ignored by synthesis tools. This also applies to part of the scheduling order problems, but some are relevant in synthesis.

§11.2 specifies:
Processes are sensitive to update events. When an update event is executed, all the processes that are sensitive to that event are evaluated in an arbitrary order.
Each process is evaluated sequentially. Because non-blocking assignments are updated after all processes are completed, scheduling order is irrelevant for them. So only in the case of blocking assignments the order matters. The cummings paper discusses some examples, they also apply to synthesized Verilog.

#### ASIC_int

##### Advanced Member level 4
FVM

Can u please send this paper of IEEE Std 1364-2005 of verilog to me with this thread. I am unable to download.

However your explnation does not answer the question strictly. The question was oes synthesis tool evaluate the always blocks one after another instead of concurrently if there are more than one always block in one module? That what we can infer from that paper from example 7 and example 8 at page 9. What do you think?

#### FvM

##### Super Moderator
Staff member
However your explnation does not answer the question strictly. The question was oes synthesis tool evaluate the always blocks one after another instead of concurrently if there are more than one always block in one module?
The single sentence from the IEEE spec already clarifies it, in my opinion.
processes that are sensitive to that event are evaluated in an arbitrary order
Consider, that a standard text is very strict. If it says, at process is evaluated, it doesn't mean, only part of the process. If it's not clear in your view, you should read the complete context.

I don't know, where you got the idea that processes may be evaluated "concurrently" in that sense, that part of one and part of another process is executed alternatingly? As far as I'm aware of, all text books tells the opposite.

edaboard rules don't allow to post officially copyright protected standards, IEEE papers, books and similar stuff. But you'll find most Verilog and VHDL standard versions downloadable at the internet.

#### ASIC_int

##### Advanced Member level 4
FVM

"processes that are sensitive to that event are evaluated in an arbitrary order"

In that case how it is written in that paper (that write of blocking and non blocking statements)in example 7 and example 8 at page 9 that the code will result in a pilelined flipflops as in Figure 2 in that paper? It is lessprobable to result in a pipelined flipflop if processes that are sensitive to that event are evaluated in an arbitrary order. In that case this paper on "blocking and non blocking statements" is wrong.

Please provide me the volume no, year and title of that paper, I will download that from IEEE as I can access IEEE.
Regards

#### FvM

##### Super Moderator
Staff member
In that case how it is written in that paper (that write of blocking and non blocking statements)in example 7 and example 8 at page 9 that the code will result in a pilelined flipflops as in Figure 2 in that paper?
It isn't written. Example 7 and 8 are designated bad blocking-assignment style, because they don't guarantee the intended pipelined result.
Please provide me the volume no, year and title of that paper, I will download that from IEEE as I can access IEEE.
I was talking about the 2005 Verilog language specification, you can also refer to other issues, because these elementary points didn't change. I quoted the full name of the standard above. If you enter it at IEEE (or google), you're directed to the document.

#### ASIC_int

##### Advanced Member level 4
" Executing the always blocks in a
different order yields a different result. However, this Verilog code will synthesize to the correct
pipeline register. This means that there might be a mismatch between the pre-synthesis and postsynthesis
simulations. The pipeb4 example, or any other ordering of the same always block
statements will also synthesize to the correct pipeline logic, but might not simulate correctly."

The above quote is directly takem from page no 9. It is written ther that "this Verilog code will synthesize to the correct
pipeline register". So you are wrong to write "It isn't written. Example 7 and 8 are designated bad blocking-assignment style, because they don't guarantee the intended pipelined result."

What is the title of the paper?

#### FvM

##### Super Moderator
Staff member
O.K., I got your point. I see two questions:
- is it always true, that the code will synthesize to the intended pipeline?
- why is it so?
I fear, the first question can't be answered exactly, at least not from the Verilog specification. I have to refer to a previous quotation:
Although the Verilog HDL is used for more than simulation, the semantics of the language are defined for simulation, and everything else is abstracted from this base definition.
In other words, the Verilog standard doesn't make any statement about synthesis behaviour.

In my opinion, the statement in the Cummings paper about correct synthesis of example 7 and 8 (and possible simulation mismatch) is based on empirical observations with existing synthesis tools, but it can't be verified in a general sense.

For the answer to the second question I have a guess: The fact, that an arbitrary evaluation order of processes is allowed opens a shortcut for the synthesis tools: They can synthesize the behaviour of blocking assignments for each process separately and don't need to keep track of the mutual dependency of processes in this regard. Thus a single blocking assignment in a process is identical to a single non-blocking one.

What is the title of the paper?
I'm referring to the IEEE Verilog specification, not a paper: IEEE Standard for Verilog Hardware Description Language - IEEE Std 1364-2005

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