Is your comment "Blocking assignments assign the value immediately, where as non blocking assignments first evaluate the value and then assigns it in the next event change" is true for simulator? Or, is it true for synthesis tool also?
However your explanation is not clear. Can u please elaborate more? The sequential circuit always evaluates the value at clock edge. How is related to blocking assignments?
I'm not sure about. May be the initial block acts as a trigger. In my opinion the self-triggering always block is rather unusual. Or as the author said "not necessarily a recommended coding style". And I wonder if it actually serves a purpose. This clk generation scheme (e.g. usable for testbenches) is suggested in the Verilog IEEE standard:It is not clear how the always block is being entered as there is no event triggering in the clock.
always begin #50 a = ~a; end
Some problems relevant for simulation are meaningless in synthesis, e.g. level sensitive events in always blocks or timed assignments (like #50 a = ~a. Both are simply ignored by synthesis tools. This also applies to part of the scheduling order problems, but some are relevant in synthesis.Although the Verilog HDL is used for more than simulation, the semantics of the language are defined for simulation, and everything else is abstracted from this base definition.
Each process is evaluated sequentially. Because non-blocking assignments are updated after all processes are completed, scheduling order is irrelevant for them. So only in the case of blocking assignments the order matters. The cummings paper discusses some examples, they also apply to synthesized Verilog.Processes are sensitive to update events. When an update event is executed, all the processes that are sensitive to that event are evaluated in an arbitrary order.
The single sentence from the IEEE spec already clarifies it, in my opinion.However your explnation does not answer the question strictly. The question was oes synthesis tool evaluate the always blocks one after another instead of concurrently if there are more than one always block in one module?
Consider, that a standard text is very strict. If it says, at process is evaluated, it doesn't mean, only part of the process. If it's not clear in your view, you should read the complete context.processes that are sensitive to that event are evaluated in an arbitrary order
It isn't written. Example 7 and 8 are designated bad blocking-assignment style, because they don't guarantee the intended pipelined result.In that case how it is written in that paper (that write of blocking and non blocking statements)in example 7 and example 8 at page 9 that the code will result in a pilelined flipflops as in Figure 2 in that paper?
I was talking about the 2005 Verilog language specification, you can also refer to other issues, because these elementary points didn't change. I quoted the full name of the standard above. If you enter it at IEEE (or google), you're directed to the document.Please provide me the volume no, year and title of that paper, I will download that from IEEE as I can access IEEE.
In other words, the Verilog standard doesn't make any statement about synthesis behaviour.Although the Verilog HDL is used for more than simulation, the semantics of the language are defined for simulation, and everything else is abstracted from this base definition.
I'm referring to the IEEE Verilog specification, not a paper: IEEE Standard for Verilog Hardware Description Language - IEEE Std 1364-2005What is the title of the paper?