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# blocking and non blocking in verilog

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#### ASIC_int

##### Advanced Member level 4
From where can I get this IEEE Standard for Verilog Hardware Description Language - IEEE Std 1364-2005 ?

What is the website where I should get the above document? How to get from there?

I am sending a message now.

#### FvM

##### Super Moderator
Staff member
From where can I get this IEEE Standard for Verilog Hardware Description Language - IEEE Std 1364-2005 ?
It's beed said
I quoted the full name of the standard above. If you enter it at IEEE (or google), you're directed to the document.
There may be different opinions about the readbility of this standard. The good thing (in my opion), it's much better understandable than the VHDL IEEE standard.

#### ASIC_int

##### Advanced Member level 4
In google if I type, it automatically take mr to IEEE. But I am inable to download the correponding pdf. So I amasking if u know the corresponding link oin IEEE.

#### FvM

##### Super Moderator
Staff member
I think, I mentioned, that the document can be found at some places, possibly academic web sites, for free download.

#### ASIC_int

##### Advanced Member level 4
I got the verilog specification file IEEE Std 1364-2001. What is the latest version. Is IEEE Std 1364-2005 the latest version?

Is that the usual books like the Verilog book by Samir Palnitkar on verilog HDL written on the basis of this specification?

#### sarandec10

##### Newbie level 1
i think this doc wil help u.

#### Attachments

• blocking-non-bloking.PDF
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#### FvM

##### Super Moderator
Staff member
Is IEEE Std 1364-2005 the latest version?
Yes, as far as I know, it's the most recent released version. But the differences to 1364-2001 are mostly neglectable, I assume, at least for scope of this discussion.

#### ASIC_int

##### Advanced Member level 4
FVM

As you wrote that Verilog language is on the basis of simulation point of view. So to conclude from this sentecnce, the evaluation of multiple always blocks in case of synthesis may not happen arbitarily. For synthesis iy may happen sequentially as described in Cummings paper. What do you think? What do u mean by that was found empirically? Do u want to mean they have taken the piperlined RTLs to tools like DC, RC Compiler and observed the result? If this is an observation then we cn conclude during synthesis lways blocks are evaluated sequentially.

What do u think?

Which field do u work in? Is it RTL Design, verification or synthesis?

Regards

#### permute

##### Advanced Member level 3
I'm fairly certain synthesis evaluates both languages with the assumption that each always block is independent. This seems very true for VHDL. Verilog, even for simulation, is specifically designed to allow the always blocks to be evaluated in parallel.

anyways, for sim "always" blocks are "always" begin evaluated. Its more obvious in this example:
Code:
always
@ (negedge rst)
req = 1;
@ (posedge ack)
req = 0;
the @ event can occur multiple times within an always block, which is more common for stimulus -- where the test source waits for some signal then continues. thus a normal always @ block does "start eval, waiting for posedge clk ... evaluate, goto beginning, line 1 is again "wait for posedge clk"."

VHDL has a similar "wait for" construct, but sensitivity lists (or single @'s for verilog) are more common.

for pipelines, I suspect a synthesizer would leave the output unregistered if the signal were used outside of the always block. I'd be interested to see what actually happens, as the blocking assign is used as the output of clock divider blocks in verilog in order to prevent simulation glitches.

#### FvM

##### Super Moderator
Staff member
I agree, that synthesis in Verilog and VHDL is similar in many regards. However, the problem mainly addressed by the cummings paper, unpredictable behaviour and simulation to synthesis mismatch related to blocking statements can't happen in VHDL, because it's equivalent to blocking statements, variable assignments, have only process local visibility.

The cummings paper is discussing, why these problem are brought up in Verilog coding, if the well-known rules are ignored. But in my opinion, there is no general problem of evaluation order besides this special point.

#### ASIC_int

##### Advanced Member level 4
FVM

Should always and initial statements be in active event region in strtified event queue? The specification file of IEEE does not mention that.

Regards

#### FvM

##### Super Moderator
Staff member
No problem I came across yet. Can you give an example which problem you have in mind?

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