Bit Width using Parameters in Verilog

[Ashish Agrawal]

Hi,

I am having a memory (depth = 64, width = parameter) to be read fully and put it in a 1-D array (width = 64*memory data width). Only 1 row can be read at a time.
This is the verilog code I have written

---

Code Verilog - [expand]
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parameter MEM_DATA_WIDTH = 32;
localparam DATA_WIDTH_O = 64*MEM_DATA_WIDTH;
 
reg [DATA_WIDTH_O -1 : 0] fsm_out;
wire [MEM_DATA_WIDTH -1 :0] mem_data_i;
reg [5:0] mem_addr;
 
///logic for generating mem_addr/////
//////////////////////////////////////////
 
always @ *
  begin
       if (valid_i)
         fsm_out [(mem_addr + 1)*MEM_DATA_WIDTH -1 : mem_addr *MEM_DATA_WIDTH]  <= mem_data_i;
  end

---

I am getting an error during compilation related to constant parameter for following operations
(mem_addr + 1)*MEM_DATA_WIDTH and mem_addr *MEM_DATA_WIDTH

Can anyone tell me how to fix this error?
Thanks in advance.

 

[FvM]

It's no legal Verilog syntax. Review your favourite Verilog text book or the LRM about indexed part select.

https://www.edaboard.com/threads/226749/

 

[Ashish Agrawal]

Can anyone help me how to fix this error if it is because of inappropriate syntax?
And if it is not just a syntax error then what should I do to get that functionality in my design?

Thanks in advance.

 

[ads-ee]

Honestly you need to write good comments in your code.
What you want is to build a demultiplexer to select the 32-bit bit slice of the 64*32-bit wide fsm_out and load your 32-bit data into it.

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Code Verilog - [expand]
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// part selects take the form:
// [lower_starting_index +: width_of_slice] or
// [upper_starting_index -: width_of_slice]
// therefore....
 
fsm_out [mem_addr*MEM_DATA_WIDTH-1 +:32] = mem_data_i; // blocking assignment as this 
                                                       // is a combinational always block

---

 

[Ashish Agrawal]

Hi ads-ee,

Your understanding is right. But the error still exists with the following operation
mem_addr*MEM_DATA_WIDTH
As MEM_DATA_WIDTH is a constant (parameter) while mem_addr is a variable (reg).

 

[ads-ee]

I just tried the following testcase using Vivado's simulator.

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Code Verilog - [expand]
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module demux #(
  parameter MEM_DATA_WIDTH = 32,
  parameter DATA_WIDTH_0 = 64*MEM_DATA_WIDTH
) (
  output reg [DATA_WIDTH_0-1:0] fsm_out,
  input [MEM_DATA_WIDTH-1:0] mem_data_i,
  input [5:0] mem_addr_i,
  input clk
);
 
reg [5:0] mem_addr;
always @ (posedge clk) mem_addr <= mem_addr_i;
 
always @* begin
  fsm_out [mem_addr*MEM_DATA_WIDTH +:MEM_DATA_WIDTH] = mem_data_i;
end
endmodule

---

and it compiles with no errors.

What simulator (and version) are you using? I know all recent Modelsim versions support it.

You might have to resort to an ugly case statement if your simulator can't support code like above:

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Code Verilog - [expand]
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always @* begin
  case (mem_addr)
    0     : fsm_out [ 0*MEM_DATA_WIDTH +:MEM_DATA_WIDTH] = mem_data_i;
    1     : fsm_out [ 1*MEM_DATA_WIDTH +:MEM_DATA_WIDTH] = mem_data_i;
    2     : fsm_out [ 2*MEM_DATA_WIDTH +:MEM_DATA_WIDTH] = mem_data_i;
    // ...
    61    : fsm_out [61*MEM_DATA_WIDTH +:MEM_DATA_WIDTH] = mem_data_i;
    62    : fsm_out [62*MEM_DATA_WIDTH +:MEM_DATA_WIDTH] = mem_data_i;
    63    : fsm_out [63*MEM_DATA_WIDTH +:MEM_DATA_WIDTH] = mem_data_i;
  endcase
end

---

BTW, the -1 in the first post for the fsm_out was a typo from cutting pasting from your original post. Sorry about that.

 

[FvM]

But the error still exists with the following operation
mem_addr*MEM_DATA_WIDTH

Your snippet compiles correctly when changed to indexed part select.

 

[Ashish Agrawal]

What simulator (and version) are you using? I know all recent Modelsim versions support it.

I am using cadence ncsim version 14.2
It might be a simulator problem as I also remember that Modelsim supports it.

BTW, can any work around be done instead of using ugly Case statement ?
I don't want to use case statement because in future mem_addr can be 10 bit also (memory depth may change), so writing 1024 case items isn't a good idea.

 

[ads-ee]

You can check the documentation for ncsim and see if it defaults to '95 support only and you need to enable 2001 support. I'd be very surprised if it really doesn't support the part select syntax.

This code also requires Verilog 2001 support.

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Code Verilog - [expand]
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integer i;
always @* begin
  for (i=0;i<64;i=i+1) begin
    if (mem_addr == i) begin
      fsm_out [i*MEM_DATA_WIDTH +: MEM_DATA_WIDTH] = mem_data_i;
    end
  end
end

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The for loop should unroll into identical code with the other versions.

You talk about this being memory, but this code probably doesn't synthesize to a memory. It doesn't conform to any standard inferred memory template. The standard templates use an array.