bidirectional data bus problem

[umerarain]

hello
iam doing my master theesis and in my theesis iam programming microprocessor using vhdl.but problem iam getting is data bus(external bus) conflict.i want to use data bus as (inout),but its not working.i have written this small program also,but its also not working.can nay one help me.

process (clk)
begin
if clk = '1' and clk 'event then
a <= Internal_bus;
b <= External_bus;

end if;
end process;

process (Output_enable,Internal_bus)
begin

if Output_enable = '1' then
External_bus <= a;

else
External_bus <= (others => 'Z');
end if;


end process;

output <= b;

 

[shankarmit]

hi u write in this way
declare internal bus as inout;

process(clk,output_enable,internal_bus)
begin
if(clk'event and clk='1')then
if(output_enable='1')then
b<=internal_bus;
elsif(output_enable='0')then
internal_bus<=a;
end if;

end if;
try this i have not checked it..

and reply me..

Regards
Shankar

 

[umerarain]

hello
i tried this one,but no result.its not working.i declared internal bus as inout ,but still same.
please help.
umer

 

[cmos babe]

How do you know it's not working? And which FPGA are you using?

 

[tkbits]

Which device is the master? I'm assuming you're not building multi-master systems.

The master must time the Output_enable signal to avoid inout conflicts with slaves. If there is more than one device on the bidirectional bus, then the slave's Output_enable must be conditioned (gated) so that only one slave will output to the master. As an example, most peripheral and memory chips have additional CE (chip enable) or CS (chip select) pins for this purpose.

If you only have two devices, and they both are masters, you should use request and acknowledge signals (handshaking).

 

[umerarain]

hi
first i try this code by using simulation software (model sim) and also by simulation waveform in xilinx.in both cases iam getting nothing on data bus when i set output_enable signal high.uptill now i havent put my code into fpga as i was not sure wheather it will work or not,any way iam using fpga of xilinx (xc2v3000).
answers will be appreciated
umer

 

[r_e_m_y]

Hi umerarain,

You should try with this code (not in a process) :
External_bus <= a when Output_enable = '1' else (others => 'Z');

If you want to keep your process, add signal a in your sensitive list.

 

[umerarain]

hi,
iam attaching two files,one is microsoft file from which you can see the structure which iam trying to make.u can see numbers written on the lines(i have problem in line number 4).and that is when iam putting my data back to data bus after alu operation.
second file is project files.please have a look
answers will be appreciated
umer