[SOLVED] Behavioral description in asic design flow

[lakshmikalyani]

Sir can you explain behavioral description in asic design flow
and
what is the difference between functional verification and logic verification in asic

 

[sam536]

Behavioral Desc : RTL can be modeled in different ways. one of them is to just to verify the understanding of your logic. write like C code and verify the idea, which cant be synthesizable. The constructs used in behavioral cant be synthesized and cant use for final ASIC signoff. Read JK bhaskar Verilog to understand more.

Functional and logic verification may be same. it used in different contexts.

 

[lakshmikalyani]

Behavioral Desc : RTL can be modeled in different ways. one of them is to just to verify the understanding of your logic. write like C code and verify the idea, which cant be synthesizable. The constructs used in behavioral cant be synthesized and cant use for final ASIC signoff. Read JK bhaskar Verilog to understand more.

Functional and logic verification may be same. it used in different contexts.

thank you sam