sunyixiang
Newbie level 1
I need to design 8 independent programmable counters by using CPLD or FPGA on a VMEbus slave. The clock frequency to these counters is 160 MHz and their N counts are programmable between 4000 to 5300. The outputs of 8 channels should be square waves with 30 - 40 kHz.
I want to design these counters by using CPLD or FPGA, is it resonable? Or you have a better idea?
If I can or have to use CPLD or FPGA, which one is better? What device do I choose? What development kit do I choose?
I am a beginner and don't know how and where I begin this project. Thanks a lot.
I want to design these counters by using CPLD or FPGA, is it resonable? Or you have a better idea?
If I can or have to use CPLD or FPGA, which one is better? What device do I choose? What development kit do I choose?
I am a beginner and don't know how and where I begin this project. Thanks a lot.